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IDT7130LA55PFGI Datasheet(PDF) 8 Page - Integrated Device Technology |
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IDT7130LA55PFGI Datasheet(HTML) 8 Page - Integrated Device Technology |
8 / 19 page IDT7130SA/LA and IDT7140SA/LA High-Speed 1K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges 8 AC Electrical Characteristics Over the Operating Temperature Supply Voltage Range(3) NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage Output Test Load (Figure 2). 2. PLCC, TQFP and STQFP packages only. 3. 'X' in part numbers indicates power rating (SA or LA). 4. This parameter is guaranteed by device characterization, but is not production tested. . 7130X20(2) 7140X20 (2) Com'l Only 7130X25 7140X25 Com'l, Ind & Military 7130X35 7140X35 Com'l & Military Unit Symbol Parameter Min.Max.Min. Max.Min.Max. READ CYCLE tRC Read Cycle Time 20 ____ 25 ____ 35 ____ ns tAA Address Access Time ____ 20 ____ 25 ____ 35 ns tACE Chip Enable Access Time ____ 20 ____ 25 ____ 35 ns tAOE Output Enable Access Time ____ 11 ____ 12 ____ 20 ns tOH Output Hold from Address Change 3 ____ 3 ____ 3 ____ ns tLZ Output Low-Z Time (1,4) 0 ____ 0 ____ 0 ____ ns tHZ Output High-Z Time (1,4) ____ 10 ____ 10 ____ 15 ns tPU Chip Enable to Power Up Time (4) 0 ____ 0 ____ 0 ____ ns tPD Chip Disable to Power Down Time(4) ____ 20 ____ 25 ____ 35 ns 2689 tbl 09a 7130X55 7140X55 Com'l, Ind & Military 7130X100 7140X100 Com'l, Ind & Military Unit Symbol Parameter Min. Max. Min. Max. READ CYCLE tRC Read Cycle Time 55 ____ 100 ____ ns tAA Address Access Time ____ 55 ____ 100 ns tACE Chip Enable Access Time ____ 55 ____ 100 ns tAOE Output Enable Access Time ____ 25 ____ 40 ns tOH Output Hold from Address Change 3 ____ 10 ____ ns tLZ Output Low-Z Time(1,4) 5 ____ 5 ____ ns tHZ Output High-Z Time(1,4) ____ 25 ____ 40 ns tPU Chip Enable to Power Up Time (4) 0 ____ 0 ____ ns tPD Chip Disable to Power Down Time(4) ____ 50 ____ 50 ns 2689 tbl 09b |
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