1-Mbit (128K x 8) Static RAM
CY62128BN
MoBL®
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
, CA 95134-1709
•
408-943-2600
Document #: 001-06498 Rev. *A
Revised August 3, 2006
Features
• Temperature Ranges
— Commercial: 0°C to 70°C
— Industrial: –40°C to 85°C
— Automotive-A: –40°C to 85°C
— Automotive-E: –40°C to 125°C
• 4.5V–5.5V operation
• CMOS for optimum speed/power
• Low active power
(70 ns Commercial, Industrial, Automotive-A)
— 82.5 mW (max.) (15 mA)
• Low standby power
(55/70 ns Commercial, Industrial, Automotive-A)
—110
µW (max.) (15 µA)
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE1, CE2, and OE options
• Available in Pb-free and non-Pb-free 32-pin (450
mil-wide) SOIC, 32-pin STSOP and 32-pin TSOP-I
Functional Description[1]
The CY62128BN is a high-performance CMOS static RAM
organized as 128K words by 8 bits. Easy memory expansion
is provided by an active LOW Chip Enable (CE1), an active
HIGH Chip Enable (CE2), an active LOW Output Enable (OE),
and
tri-state
drivers.
This
device
has
an
automatic
power-down feature that reduces power consumption by more
than 75% when deselected.
Writing to the device is accomplished by taking Chip Enable
One (CE1) and Write Enable (WE) inputs LOW and Chip
Enable Two (CE2) input HIGH. Data on the eight I/O pins (I/O0
through I/O7) is then written into the location specified on the
address pins (A0 through A16).
Reading from the device is accomplished by taking Chip
Enable One (CE1) and Output Enable (OE) LOW while forcing
Write Enable (WE) and Chip Enable Two (CE2) HIGH. Under
these conditions, the contents of the memory location
specified by the address pins will appear on the I/O pins.
The eight input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when the device is deselected (CE1
HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or
during a write operation (CE1 LOW, CE2 HIGH, and WE LOW).
Note:
1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Logic Block Diagram
A1
A2
A3
A4
A5
A6
A7
A8
COLUMN
DECODER
INPUT BUFFER
POWER
DOWN
WE
OE
I/O 0
CE2
I/O 1
I/O 2
I/O 3
128K x 8
ARRAY
I/O 7
I/O 6
I/O 5
I/O 4
A0
CE1
1
2
3
4
5
6
7
8
9
10
11
14
19
20
24
23
22
21
25
28
27
26
Top View
12
13
29
32
31
30
16
15
17
18
A16
A14
A12
A7
A6
A5
A4
A3
WE
VCC
A15
A13
A8
A9
I/O7
I/O6
I/O5
I/O4
A2
NC
I/O0
I/O1
I/O2
CE1
OE
A10
I/O3
A1
A0
A11
CE2
SOIC
GN
gnc
G
g
GND
Pin Configuration
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