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CY62167DV30 MoBL®
Document #: 38-05328 Rev. *G
Page 4 of 12
Notes:
10. Tested initially and after any design or process changes that may affect these parameters.
11. This applies for all packages.
12. Test condition for the 45 ns part is with a load capacitance of 30 pF.
13. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 100 µs or stable at VCC(min.) > 100 µs.
Capacitance[10, 11]
Parameter
Description
Test Conditions
Max.
Unit
CIN
Input Capacitance
TA = 25°C, f = 1 MHz, VCC = VCC(typ)
8pF
COUT
Output Capacitance
10
pF
Thermal Resistance[10]
Parameter
Description
Test Conditions
VFBGA
TSOP I
Unit
Θ
JA
Thermal Resistance
(Junction to Ambient)
Still Air, soldered on a 3 × 4.5 inch,
2-layer printed circuit board
55
60
°C/W
Θ
JC
Thermal Resistance
(Junction to Case)
16
4.3
°C/W
AC Test Loads and Waveforms[12]
VCC
VCC
OUTPUT
R2
50 pF[12]
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
Rise Time = 1 V/ns
Fall Time = 1 V/ns
OUTPUT
V
Equivalent to:
THEVENIN EQUIVALENT
ALL INPUT PULSES
RTH
R1
Parameters
2.5V
3.0V
Unit
R1
16667
1103
Ω
R2
15385
1554
Ω
RTH
8000
645
Ω
VTH
1.20
1.75
V
Data Retention Characteristics (Over the Operating Range)
Parameter
Description
Conditions
Min.
Typ.[2] Max.
Unit
VDR
VCC for Data Retention
1.5
V
ICCDR
Data Retention Current
VCC= 1.5V
CE1 > VCC – 0.2V, CE2 < 0.2V,
VIN > VCC – 0.2V or VIN < 0.2V
10
µA
tCDR
[10]
Chip Deselect to Data Retention Time
0
ns
tR
[13]
Operation Recovery Time
tRC
ns
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