CYRF69213
Document #: 001-07552 Rev. *B
Page 8 of 85
An RSSI reading is taken automatically when the start of a
packet is detected. In addition, a new RSSI reading is taken
every time the previous reading is read from the RSSI register,
allowing the background RF energy level on any given channel
to be easily measured when RSSI is read when no signal is
being received. A new reading can occur as fast as once every
12
µs.
SPI Interface
The SPI interface between the MCU function and the radio
function is a 3-wire SPI Interface. The three pins are MOSI
(Master Out Slave In), SCK (Serial Clock), SS (Slave Select).
There is an alternate 4-wire MISO Interface that requires the
connection of two external pins. The SPI interface is controlled
by configuring the SPI Configure Register (SICR Address:
0x3D).
3-Wire SPI Interface
The radio function receives a clock from the MCU function on
the SCK pin. The MOSI pin is multiplexed with the MISO pin.
Bidirectional data transfer takes place between the MCU
function and the radio function through this multiplexed MOSI
pin. When using this mode the user firmware should ensure
that the MOSI pin on the MCU function is in a high impedance
state, except when the MCU is actively transmitting data.
Firmware must also control the direction of data flow and
switch directions between MCU function and radio function by
setting the SWAP bit [Bit 7] of the SPI Configure Register. The
SS pin is asserted prior to initiating a data transfer between the
MCU function and the radio function. The IRQ function may be
optionally multiplexed with the MOSI pin; when this option is
enabled the IRQ function is not available while the SS pin is
low. When using this configuration, user firmware should
ensure that the MOSI function on MCU function is in a
high-impedance state whenever SS is high.
Figure 4. 3-Wire SPI Mode
4-Wire SPI Interface
The 4-wire SPI communications interface consists of MOSI,
MISO, SCK, and SS.
The device receives SCK from the MCU function on the SCK
pin. Data from the MCU function is shifted in on the MOSI pin.
Data to the MCU function is shifted out on the MISO pin. The
active low SS pin must be asserted for the two functions to
communicate. The IRQ function may be optionally multiplexed
with the MOSI pin; when this option is enabled the IRQ
function is not available while the SS pin is low. When using
this configuration, user firmware should ensure that the MOSI
function on MCU function is in a high-impedance state
whenever SS is high.
Figure 5. 4-WIRE SPI Mode
SPI Communication and Transactions
The SPI transactions can be single byte or multi-byte. The
MCU
function
initiates
a
data
transfer
through
a
Command/Address byte. The following bytes are data bytes.
The SPI transaction format is shown in Figure 6.
The DIR bit specifies the direction of data transfer. 0 = Master
reads from slave. 1 = Master writes to slave.
The INC bit helps to read or write consecutive bytes from
contiguous memory locations in a single burst mode
operation.
If Slave Select is asserted and INC = 1, then the master MCU
function reads a byte from the radio, the address is incre-
mented by a byte location, and then the byte at that location is
read, and so on.
If Slave Select is asserted and INC = 0, then the MCU function
reads/writes the bytes in the same register in burst mode, but
if it is a register file then it reads/writes the bytes in that register
file.
The SPI interface between the radio function and the MCU is
not dependent on the internal 12-MHz oscillator of the radio.
Therefore, radio function registers can be read from or written
into while the radio is in sleep mode.
SPI IO Voltage References
The SPI interfaces between MCU function and the radio and
the IRQ and RST have a separate voltage reference VIO,
enabling the radio function to directly interface with the MCU
MCU Function
P1.5/MOSI
P1.4/SCK
P1.3/nSS
MOSI
SCK
nSS
Radio Function
MOSI/MISO multiplexed
on one MOSI pin
MCU Function
P1.5/MOSI
P1.4/SCK
P1.3/nSS
P1.6/MISO
MOSI
SCK
nSS
Radio Function
MISO
This connection is external to the PRoC LP Chip
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