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CYS25G0101DX
Document Number: 38-02009 Rev. *K
Page 11 of 17
AC Specifications
Table 6. AC Specifications—Parallel Interface
Parameter
Description
Min
Max
Unit
tTS
TXCLKI Frequency (must be frequency coherent to REFCLK)
154.5
156.5
MHz
tTXCLKI
TXCLKI Period
6.38
6.47
ns
tTXCLKID
TXCLKI Duty Cycle
40
60
%
tTXCLKIR
TXCLKi Rise Time
0.3
1.5
ns
tTXCLKIF
TXCLKi Fall Time
0.3
1.5
ns
tTXDS
Write Data Setup to
↑ of TXCLKI
1.5
ns
tTXDH
Write Data Hold from
↑ of TXCLKI
0.5
ns
tTOS
TXCLKO Frequency
154.5
156.5
MHz
tTXCLKO
TXCLKO Period
6.38
6.47
ns
tTXCLKOD
TXCLKO Duty Cycle
43
57
%
tTXCLKOR
TXCLKO Rise Time
0.3
1.5
ns
tTXCLKOF
TXCLKO Fall Time
0.3
1.5
ns
tRS
RXCLK Frequency
154.5
156.5
MHz
tRXCLK
RXCLK Period
6.38
6.47
ns
tRXCLKD
RXCLK Duty Cycle
43
57
%
tRXCLKR
RXCLK Rise Time[6]
0.3
1.5
ns
tRXCLKF
RXCLK Fall Time[6]
0.3
1.5
ns
tRXDS
Recovered Data Setup with reference to
↑ of RXCLK
2.2
ns
tRXDH
Recovered Data Hold with reference to
↑ of RXCLK
2.2
ns
tRXPD
Valid Propagation Delay
–1.0
1.0
ns
Table 7. AC Specifications—REFCLK
The AC Specifications—REFCLK follow. [7]
Parameter
Description
Min
Max
Unit
tREF
REFCLK Input Frequency
154.5
156.5
MHz
tREFP
REFCLK Period
6.38
6.47
ns
tREFD
REFCLK Duty Cycle
35
65
%
tREFT
REFCLK Frequency Tolerance — (relative to received serial data)[8]
–100
+100
ppm
tREFR
REFCLK Rise Time
0.3
1.5
ns
tREFF
REFCLK Fall Time
0.3
1.5
ns
Table 8. AC Specifications–CML Serial Outputs
Parameter
Description
Min
Typical
Max
Unit
tRISE
CML Output Rise Time (20–80%, 100
Ω balanced load)
60
170
ps
tFALL
CML Output Fall Time (80–20%, 100
Ω balanced load)
60
170
ps
Notes
6. RXCLk rise time and fall times are measured at the 20 to 80 percentile region of the rising and falling edge of the clock signal.
7. The 155.52 MHz Reference Clock Phase Noise Limits for the CYS25G0101DX are shown in Figure 6.
8. +20 ppm is required to meet the SONET output frequency specification.