CYV15G0104TRB
Document #: 38-02100 Rev. *C
Page 11 of 28
the true or complement REFCLKB input, and leave the
alternate REFCLKB input open (floating).
When both the REFCLKB+ and REFCLKB– inputs are
connected, the clock source must be a differential clock. This
can either be a differential LVPECL clock that is DC- or
AC-coupled or a differential LVTTL or LVCMOS clock.
By connecting the REFCLKB– input to an external voltage
source, it is possible to adjust the reference point of the
REFCLKB+ input for alternate logic levels. When doing so, it
is necessary to ensure that the input differential crossing point
remains within the parametric range supported by the input.
Transmit Serial Output Drivers
The serial output interface drivers use differential Current
Mode Logic (CML) drivers to provide source-matched drivers
for 50
Ω transmission lines. These drivers accept data from the
transmit shifter. These drivers have signal swings equivalent
to that of standard PECL drivers, and are capable of driving
AC-coupled optical modules or transmission lines.
Transmit Channels Enabled
Each driver can be enabled or disabled separately via the
device configuration interface.
When a driver is disabled via the configuration interface, it is
internally powered down to reduce device power. If both
transmit serial drivers are in this disabled state, the transmitter
internal logic for that channel is also powered down. A device
reset (RESET sampled LOW) disables all output drivers.
Note. When the disabled transmit channel (i.e., both outputs
disabled) is re-enabled:
• the data on the transmit serial outputs may not meet all
timing specifications for up to 250
μs
• the state of the phase-align buffer cannot be guaranteed,
and a phase-align reset is required if the phase-align buffer
is used
CYV15G0104TRB Receive Data Path
Serial Line Receivers
Two differential Line Receivers, INA1± and INA2±, are
available on the receive channel for accepting serial data
streams. The active Serial Line Receiver is selected using the
INSELA input. The Serial Line Receiver inputs are differential,
and can accommodate wire interconnect and filtering losses
or transmission line attenuation greater than 16 dB. For
normal operation, these inputs should receive a signal of at
least VIDIFF > 100 mV, or 200 mV peak-to-peak differential.
Each Line Receiver can be DC- or AC-coupled to +3.3V
powered fiber-optic interface modules (any ECL/PECL family,
not limited to 100K PECL) or AC-coupled to +5V powered
optical modules. The common-mode tolerance of these line
receivers accommodates a wide range of signal termination
voltages. Each receiver provides internal DC-restoration, to
the center of the receiver’s common mode range, for
AC-coupled signals.
Signal Detect/Link Fault
Each selected Line Receiver (i.e., that routed to the clock and
data recovery PLL) is simultaneously monitored for
• analog amplitude above amplitude level selected by
SDASELA
• transition density above the specified limit
• range controls report the received data stream inside
normal frequency range (±1500 ppm[24])
• receive channel enabled
• Presence of reference clock
•ULCA is not asserted.
All of these conditions must be valid for the Signal Detect block
to indicate a valid signal is present. This status is presented on
the LFIA (Link Fault Indicator) output associated with each
receive channel, which changes synchronous to the receive
interface clock.
Analog Amplitude
While most signal monitors are based on fixed constants, the
analog amplitude level detection is adjustable to allow
operation with highly attenuated signals, or in high-noise
environments. The analog amplitude level detection is set by
the SDASELA latch via device configuration interface. The
SDASELA latch sets the trip point for the detection of a valid
signal at one of three levels, as listed in Table 2. This control
input affects the analog monitors for all receive channels. The
Analog Signal Detect monitors are active for the Line Receiver
as selected by the INSELA input.
Transition Density
The Transition Detection logic checks for the absence of
transitions spanning greater than six transmission characters
(60 bits). If no transitions are present in the data received, the
Detection logic for that channel asserts LFIA.
Range Controls
The CDR circuit includes logic to monitor the frequency of the
PLL Voltage Controlled Oscillator (VCO) used to sample the
incoming data stream. This logic ensures that the VCO
operates at, or near the rate of the incoming data stream for
two primary cases:
• when the incoming data stream resumes after a time in
which it has been “missing.”
• when the incoming data stream is outside the acceptable
signaling rate range.
Table 2. Analog Amplitude Detect Valid Signal Levels[7]
SDASELA
Typical Signal with Peak Amplitudes
Above
00
Analog Signal Detector is disabled
01
140 mV p-p differential
10
280 mV p-p differential
11
420 mV p-p differential
Note
7. The peak amplitudes listed in this table are for typical waveforms that have generally 3–4 transitions for every ten bits. In a worse case environment the signals
may have a sine-wave appearance (highest transition density with repeating 0101...). Signal peak amplitudes levels within this environment type could increase
the values in the table above by approximately 100 mV.
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