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AD7767 Datasheet(PDF) 6 Page - Analog Devices |
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AD7767 Datasheet(HTML) 6 Page - Analog Devices |
6 / 24 page AD7767 Rev. 0 | Page 6 of 24 TIMING DIAGRAMS MCLK 1 DRDY t2 t3 t4 t1 tREAD t5 t5 tDRDY 8 × n 8 × n 1 Figure 2. DRDY vs. MCLK Timing Diagram, n = 1 for AD7767 (Decimate by 8), n = 2 for AD7767-1 (Decimate by 16), n = 4 for AD7767-2 (Decimate by 32) DRDY CS SCLK SDO tDRDY tREAD D22 MSB D21 D20 D1 LSB t6 t13 t12 1 23 t10 t11 t7 t8 t9 Figure 3. Serial Timing Diagram, Reading Data Using CS CS = 0 SCLK SDO DATA INVALID MSB D22 D21 D20 D1 LSB DATA INVALID DRDY tDRDY tREAD 1 23 24 t14 t8 t9 t15 t11 t10 Figure 4. Serial Timing Diagram, Reading Data Setting CS Logic Low |
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