CYIS1SM0250-AA
Document Number: 38-05713 Rev. *B
Page 11 of 24
Programmable Gain Amplifier
The signal from the column amplifiers is fed to an output
amplifier with four presettable gains (adjustable with pins G0
and G1). The offset correction of this amplifier is done through
a black reference procedure. The signal from the output
amplifier is externally available on the analog output
terminator of the device.
Analog-to-Digital Converter
The on-chip 10-bit ADC is electrically separated from the other
circuits of the device. The ADC conversion range is set by the
voltages on VLOW_ADC (pin 47) and VHIGH_ADC (pin 70).
Make voltages on these pins equal to about 2V on
VLOW_ADC and 4V on VHIGH_ADC. The voltages are set by
connecting VLOW with 1.2k
Ω to GND and VHIGH_ADC with
560
Ω to VDD. This way, a resistor ladder is created as shown
in Figure 9.
Figure 9. ADC Resistor Ladder
The internal ADC resistance varies according to temperature.
The resistance value increases approximately 4.4
Ω/°C with
increasing temperature. If the ADC range is set externally with
resistors, the conversion range may vary with temperature.
This effect is cancelled out by not making use of resistors but
directly applying voltages on VLOW_ADC and VHIGH_ADC.
Timing and Readout of the Image Sensor
Image Readout Procedure
A preamble or initialization phase is irrelevant. The sensor is
read out continuously. The first frame is generally saturated
and useless because there is no preceding reset of each pixel.
Image Readout
In an infinite uninterrupted loop, follow these steps line-by-line:
1. Synchronize the read (YL) and/or reset (YR) registers, in
this cases:
• SYNC_YL - to reinitiate the readout sequence to row
position Y1
• SYNC_YR - to reinitiate the reset pointer to row position
Y1
For all other lines do not pulse one of these SYNC_Y signals.
2. Operate the double sampling column amplifiers with two
RESETs. Apply one to reset the line that is currently
selected to produce the reset reference level for the double
sampling column amplifiers. Apply the other reset to
another line depending on the required integration time
reduction.
3. Perform a Line Readout:
Reset the X read address shift register to the value in its
shadow register (X1).
Perform a pixel readout operation, operating the track/hold
and the ADC.
Shift the X read address shift register one position further.
Shift the Y read and reset address shift registers one position
further. If either of Y read or reset address shift register comes
to the end of the pixel array (or the ROI), wrap it around to the
start position by pulsing SYNC_YL.
Readout Timing
The actual line readout process starts with addressing the line
to read. This is done either by initializing the YL pointer with a
new value, or by shifting it one position beyond its previous
value. (Addressing the line has reset, YR is done in an
analogous fashion). During the "blanking time", after the new
line is addressed on the sensor, the built-in column-parallel
double sampling amplifiers are operated. This renders
offset-corrected values of the line under readout.
After the blanking time the pixels of the row addressed by YL
are read by multiplexing all the pixels one by one to the serial
output chain. The pixel is selected by the X pointer, and that
pointer is either initialized with a new value or an increment of
the previous position.
The time between row resets and their corresponding row
readouts is the effective exposure time (or integration time).
This time is proportional to the number of lines (DelayLines)
between the line currently under reset and the line currently
under readout: DelayLines = (YR - YL+1). This time is also
equal to the delay between the SYNC_YR pulse and the
subsequent SYNC_YR.
The effective integration time tint is calculated as delaylines *
line time. The line time itself is a function of four terms: the time
to output the desired number of pixels in the line (Wframe), and
the overhead ("blanking") time that is needed to select an new
line and perform the double sampling and reset operations.
RADC_VHIGH
External
Internal
RADC
RADC_VLOW
External
Pin 70: VHIGH_ADC
Pin 47: VLOW_ADC
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