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PCA9675DK Datasheet(PDF) 6 Page - NXP Semiconductors |
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PCA9675DK Datasheet(HTML) 6 Page - NXP Semiconductors |
6 / 34 page PCA9675_1 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 01 — 1 February 2007 6 of 34 NXP Semiconductors PCA9675 Remote 16-bit I/O expander for Fm+ I2C-bus with interrupt [1] HVQFN and DHVQFN package die supply ground is connected to both the VSS pin and the exposed center pad. The VSS pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board-level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board, and for proper heat conduction through the board thermal vias need to be incorporated in the PCB in the thermal pad region. 7. Functional description Refer to Figure 1 “Block diagram of PCA9675”. 7.1 Device address Following a START condition, the bus master must send the address of the slave it is accessing and the operation it wants to perform (read or write). The address of the PCA9675 is shown in Figure 9. Slave address pins AD2, AD1, and AD0 choose 1 of 64 slave addresses. To conserve power, no internal pull-up resistors are incorporated on AD2, AD1, and AD0. Address values depending on AD2, AD1, and AD0 can be found in Table 3 “PCA9675 address map”. Remark: The General Call address (0000 0000b) and the Device ID address (1111 100Xb) are reserved and cannot be used as device address. Failure to follow this requirement will cause the PCA9675 not to acknowledge. Remark: Reserved I2C-bus addresses must be used with caution since they can interfere with: • “reserved for future use” I2C-bus addresses (0000 011, 1111 101, 1111 110, 1111 111) • slave devices that use the 10-bit addressing scheme (1111 0xx) • High speed mode (Hs-mode) master code (0000 1xx) The last bit of the first byte defines the operation to be performed. When set to logic 1 a read is selected, while a logic 0 selects a write operation. When AD2, AD1 and AD0 are held to VDD or VSS, the same address as the PCF8575 is applied. SCL 22 19 serial clock line input SDA 23 20 serial data line input/output VDD 24 21 supply voltage Table 2. Pin description …continued Symbol Pin Description SO, SSOP, TSSOP, DHVQFN HVQFN Fig 9. PCA9675 address R/W 002aab636 A6 A5 A4 A3 A2 A1 A0 programmable slave address |
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