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RM5231A-300-H Datasheet(PDF) 10 Page - PMC-Sierra, Inc |
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RM5231A-300-H Datasheet(HTML) 10 Page - PMC-Sierra, Inc |
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10 / 40 page  Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use 10 Document ID: PMC-2002174, Issue 2 RM5231A™ Microprocessor with 32-Bit System Bus Data Sheet Preliminary 2 Block Diagram Figure 1 Block Diagram Integer Address/Adder Instruction Dispatch Unit Primary Data Cache 2-way Set Associative Primary Instruction Cache 2-way Set Associative DTag DTLB ITag ITLB FP Instruction Register Integer Instruction Register Store Buffer Write Buffer Read Buffer Pad Buffer Address Buffer Load Aligner Integer Register File DTLB Virtual PLL/Clocks Floating-Point Load/Align Floating-Point Register File Packer/Unpacker Floating-Point MultAdd, Add, Sub, Cvt, Div, Sqrt Joint TLB Coprocessor 0 System/Memory Control PC Incrementer Branch PC Adder ITLB Virtual Program Counter Int Mult, Div, Madd DVA IVA Pad Bus D Bus FP Bus Integer Bus FA Bus A/D Bus Shifter/Store Aligner Logic Unit |
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