Electronic Components Datasheet Search |
|
RM7000B Datasheet(PDF) 1 Page - PMC-Sierra, Inc |
|
RM7000B Datasheet(HTML) 1 Page - PMC-Sierra, Inc |
1 / 2 page RM7000B Preliminary 64-Bit MIPS RISC Microprocessor with Integrated L2 Cache PMC- 2011603(P1) PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE © Copyright PMC-Sierra, Inc. 2000 FEATURES • Dual-Issue symmetric superscalar microprocessor • 500MHz max CPU frequency • Capable of issuing two instructions per clock cycle • Integrated primary and secondary caches • 16KB Instruction, 16KB Data, and 256KB on-chip secondary • All are 4-way set associative with 32-byte line size • Per-line locking in primary and secondary caches • Fast Packet Cache™ increases system efficiency in networking applications • Integrated external cache controller • Allows up to 8Mbyte of external cache for applications with large data sets • High-performance system interface • 1000 Mbyte per-second peak throughput • 125 MHz max. freq., multiplexed address/data bus (SysAD) • Supports two outstanding reads with out-of-order return • High-performance floating-point unit • 1000 MFLOPS maximum • IEEE754 compliant single and double precision floating-point operations • 64-bit MIPS instruction set architecture • Data PREFETCH instruction allows the processor to overlap cache miss latency and instruction execution • Single-cycle floating-point multiply- add • Integrated memory management unit • Fully associative TLB • 64/48 dual entries map 128/96 pages • Variable page size • Embedded application enhancements • Fourteen fully prioritized vectored interrupts-10 external, 2 internal, 2 software • Specialized DSP integer Multiply- Accumulate instructions (MAD/MADU), and three-operand Multiply instruction (MUL) • I and D Test/Break-point (Watch) registers for emulation and debug • Performance counter for system and software tuning and debug PACKAGING • Fully Static 0.13µ CMOS design with dynamic power down logic • 304 pin TBGA package, 31x31 mm DEVELOPMENT TOOLS • Operating Systems: • Linux by MontaVista and Red Hat • VxWorks by Wind River Systems • Nucleus by Accelerated Technology • Neutrino by QNX Software Systems • Compiler Suites • Algorithmics • Green Hills Software BLOCK DIAGRAM 64-bit Integer Unit Dual-Issue Superscalar 64-bit FP Unit Double/Single IEEE754 Integer Multiplier D-Cache 16KB, 4-way, lockable I-Cache 16KB, 4-way, lockable System Control PC Unit MMU Fully Assoc., 48 or 64 Entry Bus Interface Unit L3 Cache Control Instr. Dispatch SysA /D Bus & L3 Ctr System Cache (L2) 256KB, 4-way, lockable Int Ctlr NMI, INT9 – INT0 64-bit |
Similar Part No. - RM7000B |
|
Similar Description - RM7000B |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |