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PS21964-AT Datasheet(PDF) 6 Page - Mitsubishi Electric Semiconductor |
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PS21964-AT Datasheet(HTML) 6 Page - Mitsubishi Electric Semiconductor |
6 / 10 page MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module> PS21964-T/-AT/-CT/-TW TRANSFER-MOLD TYPE INSULATED TYPE Aug. 2007 6 Note 8: Flatness measurement position +– + – Heat sink side Heat sink side 4.6mm DIP-IPM Measurement position Mounting screw : M3 (Note 7) Condition Parameter Limits Mounting torque Weight Heat-sink flatness Min. MECHANICAL CHARACTERISTICS AND RATINGS Typ. Max. 0.59 — –50 Unit — 10 — 0.78 — 100 N·m g µm Recommended : 0.69 N·m (Note 8) Note 7 : Plain washers (ISO 7089~7094) are recommended. CONTROL (PROTECTION) PART Symbol ID VFOH VFOL VSC(ref) IIN OTt OTrh UVDBt UVDBr UVDt UVDr tFO Vth(on) Vth(off) Vth(hys) Parameter Condition Limits Unit Circuit current Fault output voltage Short circuit trip level Control supply under-voltage protection Fault output pulse width ON threshold voltage OFF threshold voltage ON/OFF threshold hysteresis voltage VD = VDB = 15V VIN = 5V Total of VP1-VNC, VN1-VNC VUFB-U, VVFB-V, VWFB-W VSC = 0V, FO terminal pull-up to 5V by 10k Ω VSC = 1V, IFO = 1mA Tj = 25 °C, VD = 15V (Note 4) VIN = 5V Trip level Trip/reset hysteresis Trip level Reset level Trip level Reset level (Note 6) Applied between UP, VP, WP, UN, VN, WN-VNC — — — — 4.9 — 0.43 0.70 100 — 10.0 10.5 10.3 10.8 20 — 0.8 0.35 — — — — — — 0.48 1.00 120 10 — — — — — 2.1 1.3 0.65 2.80 0.55 2.80 0.55 — 0.95 0.53 1.50 140 — 12.0 12.5 12.5 13.0 — 2.6 — — Min. Typ. Max. mA mA mA mA V V V mA °C V V V V µs V V V VD = VDB = 15V VIN = 0V Total of VP1-VNC, VN1-VNC VUFB-U, VVFB-V, VWFB-W Tj ≤ 125°C Input current Note 4 : Short circuit protection is functioning only for the lower-arms. Please select the external shunt resistance such that the SC trip-level is less than 1.7 times of the current rating. 5: Over temperature protection (OT) outputs fault signal, when the LVIC temperature exceeds OT trip temperature level (OTt). In that case if the heat sink comes off DIP-IPM or fixed loosely, don’t reuse that DIP-IPM. (There is a possibility that junction temperature of power chips exceeded maximum Tj (150 °C)). 6: Fault signal is asserted only corresponding to a SC, a UV or an OT failure at lower side, and the FO pulse width is different for each fail- ure modes. For SC failure, FO output is with a fixed width of 20 µsec(min), but for UV or OT failure, FO output continuously during the whole UV or OT period, however, the minimum FO pulse width is 20 µsec(min) for very short UV or OT period less than 20µsec. Over temperature protection (Note 5) VD = 15V, At temperature of LVIC |
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