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RECEIVE MODE

PARITY ERROR DETECTION AND HANDLING

R[0:7],G[0:7],

B[0:7],HS,VS,DE

PCLK

(CPOL=0)

CPE

Whenaparityerroris

detected,thereceiveroutputs

thepreviouspixelonthebus

Hencenodatatransitions

occur.

A Parityerrorisindicatedbya

highpulseonCPE;thewidthof

thepulseis1/2thelengthofa

PCLKcycle

Alsoifthereisaparityerrordetectedthenthe

dataonthatPCLKcycleisnotoutput.Instead,

thelastvaliddatafromapreviousPCLKcycle

isrepeatedontheoutputbus. Thisistoprevent

anybiterrorthatmayoccurontheLVDSlink

fromcausingperturbationsinVS,HS,orDEthat

maybevisuallydisruptivetoadisplay.

Thereservedbitsarenotcoveredintheparity

calculations.

SN65LVDS302

SLLS733B – JUNE 2006 – REVISED FEBRUARY 2007

the SN65LVDS302 PLL is enabled. Under such conditions, it is possible for the PLL to lock temporarily to the

pixel clock, causing the PLL monitor to release the device into active receive mode. If this happens, the PLL

may or may not be properly locked to the pixel clock input, potentially causing data errors, frequency oscillation,

and PLL deadlock (loss of VCO oscillation).

After the PLL achieves lock the device enters the normal receive mode. The output data bus presents the

de-serialized data. The PCLK output pin outputs the recovered pixel clock.

The SN65LVDS302 receiver performs error checking on the basis of a parity bit that is transmitted across the

subLVDS interface from the transmitting device. Once the SN65LVDS302 detects the presence of the clock and

the PLL has locked onto PCLK, then the parity is checked. Parity-error detection ensures detection of all single

bit errors in one pixel and 50% of all multi-bit errors.

The parity bit covers the 27 bit data payload consisting of 24 bits of pixel data plus VS, HS, and DE. Odd Parity

bit signalling is used. The parity error is output on the CPE pin. If the sum of the 27 data bits and the parity bit

result in an odd number, the receive data are assumed to be valid. The CPE output will be held low. If the sum

equals an even number, parity error is declared. The CPE output will indicate high for half a PCLK period. The

CPE output will be set with the data bit transition and cleared after 1/2 the data bit time. This allows counting

every detected parity error with a simple counter connected to CPE.

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