BH62UV4000SI55 datasheet(4/12 Pages) BSI

Part #	BH62UV4000SI55

Description	Ultra Low Power/High Speed CMOS SRAM 512K X 8 bit

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Manufacturer	BSI [Brilliance Semiconductor]

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BH62UV4000

R0201-BH62UV4000

Revision

1.2

Aug.

2006

4

n AC TEST CONDITIONS

(Test Load and Input/Output Reference)

Input Pulse Levels

VCC / 0V

Input Rise and Fall Times

1V/ns

Input and Output Timing

Reference Level

0.5Vcc

tCLZ1, tCLZ2, tOLZ, tCHZ1,

tCHZ2, tOHZ, tWHZ, tOW

CL = 5pF+1TTL

Output Load

Others

CL = 30pF+1TTL

1. Including jig and scope capacitance.

n KEY TO SWITCHING WAVEFORMS

WAVEFORM

INPUTS

OUTPUTS

MUST BE

STEADY

MUST BE

STEADY

MAY CHANGE

FROM

“H” TO “L”

WILL BE CHANGE

FROM

“H” TO “L”

MAY CHANGE

FROM

“L” TO “H”

WILL BE CHANGE

FROM

“L” TO “H”

DON

’T CARE

ANY CHANGE

PERMITTED

CHANGE :

STATE UNKNOW

DOES NOT

APPLY

CENTER LINE IS

HIGH INPEDANCE

“OFF” STATE

n AC ELECTRICAL CHARACTERISTICS (T

A = -40

OC to +85OC)

READ CYCLE

CYCLE TIME : 55ns

JEDEC

PARAMETER

NAME

PARANETER

NAME

DESCRIPTION

MIN.

TYP.

MAX.

UNITS

tAVAX

tRC

Read Cycle Time

55

--

ns

tAVQX

tAA

Address Access Time

--

55

ns

tE1LQV

tACS

Chip Select Access Time

--

55

ns

tGLQV

tOE

Output Enable to Output Valid

--

30

ns

tE1LQX

tCLZ

Chip Select to Output Low Z

10

--

ns

tGLQX

tOLZ

Output Enable to Output Low Z

10

--

ns

tE1HQZ

tCHZ

Chip Select to Output High Z

--

30

ns

tGHQZ

tOHZ

Output Enable to Output High Z

--

25

ns

tAVQX

tOH

Data Hold from Address Change

10

--

ns

n SWITCHING WAVEFORMS (READ CYCLE)

READ CYCLE 1

(1,2,4)

CL

(1)

1 TTL

Output

ALL INPUT PULSES

→ ←

90%

VCC

GND

Rise Time:

1V/ns

Fall Time:

1V/ns

90%

→ ←

10%

tRC

tOH

tAA

DOUT

ADDRESS

tOH

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