Ultra Low Power/High Speed CMOS SRAM

512K X 16 bit

BH616UV8010

R0201-BH616UV8010

Revision

1.2

May.

2006

1

Pb-Free and Green package materials are compliant to RoHS

n FEATURES

Ÿ Wide V

Ÿ Ultra low power consumption :

Operation current : 12mA (Max.)at 55ns

2mA (Max.)at 1MHz

Standby current : 2.5uA (Typ.) at 3.0V/25

Data retention current : 1.2uA (Typ.) at 25

Ÿ High speed access time :

-55

-70

Ÿ Automatic power down when chip is deselected

Ÿ Easy expansion with CE1, CE2 and OE options

Ÿ I/O Configuration x8/x16 selectable by LB and UB pin.

Ÿ Three state outputs and TTL compatible

Ÿ Fully static operation, no clock, no refresh

Ÿ Data retention supply voltage as low as 1.0V

n DESCRIPTION

The BH616UV8010 is a high performance, ultra low power CMOS

Static Random Access Memory organized as 524,288 by 16 bits and

operates in a wide range of 1.65V to 3.6V supply voltage.

Advanced CMOS technology and circuit techniques provide both

high speed and low power features with typical operating current of

1.5mA at 1MHz at 3.6V/25

1.65V/85

Easy memory expansion is provided by an active LOW chip enable

(CE1), an active HIGH chip enable (CE2) and active LOW output

enable (OE) and three-state output drivers.

The BH616UV8010 has an automatic power down feature, reducing

the power consumption significantly when chip is deselected.

The BH616UV8010 is available in DICE form, JEDEC standard

48-pin TSOP-I and 48-ball BGA package.

n POWER CONSUMPTION

POWER DISSIPATION

STANDBY

Operating

PRODUCT

FAMILY

OPERATING

TEMPERATURE

1MHz

10MHz

1MHz

10MHz

PKG TYPE

BH616UV8010DI

DICE

BH616UV8010AI

BGA-48-0608

BH616UV8010TI

Industrial

-40

15uA

12uA

2mA

6mA

12mA

1.5mA

5mA

8mA

TSOP I-48

n PIN CONFIGURATIONS

n BLOCK DIAGRAM

Detailed product characteristic test report is available upon request and being accepted.

G

H

F

E

D

C

B

A

1

2

3

4

5

6

A9

A11

A10

NC

A12

A14

A13

A15

WE

DQ13

DQ5

DQ7

DQ6

A17

A16

A7

VSS

VCC

DQ12

DQ11

DQ4

DQ3

VSS

A5

OE

A3

A0

A6

A4

A1

A2

CE2

UB

DQ10

DQ1

CE1

DQ2

DQ0

48-ball BGA top view

LB

DQ8

DQ9

VSS

VCC

DQ14

DQ15

A18

NC

A8

A15

A14

A13

A12

A11

A10

A9

A8

NC

NC

WE

CE2

NC

UB

LB

A18

A17

A7

A6

A5

A4

A3

A2

A1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

BH616UV8010TI

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

A16

NC

VSS

DQ15

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

VCC

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

OE

VSS

CE1

A0

Address

Input

Buffer

Row

Decoder

Memory Array

1024 x 8192

Column I/O

Write Driver

Sense Amp

Column Decoder

Address Input Buffer

A15

A16 A2 A1

Data

Input

Buffer

Control

DQ0

.

.

.

.

.

.

DQ15

A12

A11

A10

A9

A8

A7

A6

A5

A4

A3

16

16

16

16

9

512

8192

1024

10

A18

Data

Output

Buffer

A13

CE2

CE1

WE

OE

UB

LB

A0

.

.

.

.

.

.

A14

A17