BS62LV8001

R0201-BS62LV8001

Revision

2.3

May.

2006

7

WRITE CYCLE 2

(1,6)

NOTES:

1. WE must be high during address transitions.

2. The internal write time of the memory is defined by the overlap of CE1 and CE2 active and

WE low. All signals must be active to initiate a write and any one signal can terminate a

write by going inactive. The data input setup and hold timing should be referenced to the

second transition edge of the signal that terminates the write.

write cycle.

4. During this period, DQ pins are in the output state so that the input signals of opposite

phase to the outputs must not be applied.

5. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low

transitions or after the WE transition, output remain in a high impedance state.

9. If CE1 is low and CE2 is high during this period, DQ pins are in the output state. Then the

data input signals of opposite phase to the outputs must not be applied to them.

The parameter is guaranteed but not 100% tested.

(11)

(11)

(2)

(4,10)

(3)

WE

CE2

CE1

ADDRESS

(5)

(5)

(7)

(8)

(8,9)