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MT48H16M16LFB5-75ITG Datasheet(PDF) 6 Page - Micron Technology |
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MT48H16M16LFB5-75ITG Datasheet(HTML) 6 Page - Micron Technology |
6 / 71 page PDF:09005aef8219eeeb/Source: 09005aef8219eedd Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H16M16LF_2.fm - Rev F 4/07 EN 6 ©2006 Micron Technology, Inc. All rights reserved. 256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM Functional Block Diagrams The 256Mb SDRAM is designed to operate in 1.8V low-power memory systems. An auto refresh mode is provided, along with a power-saving deep power-down mode. All inputs and outputs are LVTTL-compatible. SDRAM offers substantial advances in DRAM operating performance, including the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks in order to hide precharge time, and the capability to randomly change column addresses on each clock cycle during a burst access. Functional Block Diagrams Figure 2: 16 Meg x 16 SDRAM 13 RAS# CAS# ROW- ADDRESS MUX CLK CS# WE# CKE CONTROL LOGIC COLUMN- ADDRESS COUNTER/ LATCH MODE REGISTER 9 A0–A12, BA0, BA1 UDQM, LDQM 13 ADDRESS REGISTER 15 256 (x16) 8,192 I/O GATING DQM MASK LOGIC READ DATA LATCH WRITE DRIVERS COLUMN DECODER BANK0 MEMORY ARRAY (8,192 x 512 x 16) BANK0 ROW- ADDRESS LATCH & DECODER 8,192 Sense amplifiers BANK CONTROL LOGIC DQ0– DQ15 16 16 15 Bank1 Bank2 Bank3 13 9 2 2 2 2 REFRESH COUNTER EXT MODE REGISTER 16 BA1 BA0 Bank 0 0 0 0 1 1 1 0 2 1 1 3 DATA OUTPUT REGISTER DATA INPUT REGISTER |
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