TSL2014

896 y 1 LINEAR SENSOR ARRAY

TAOS040B − MAY 2007

4

r

r

Copyright E 2007, TAOS Inc.

The LUMENOLOGY r Company

www.taosinc.com

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Analog output voltage (white, average over 896 pixels) See Note 1

1.6

2

2.4

V

Analog output voltage (dark, average over 896 pixels)

0

0.05

0.15

V

PRNU

Pixel response nonuniformity

See Notes 2 & 3

7%

20%

Nonlinearity of analog output voltage

See Note 3

± 0.4%

FS

Output noise voltage

See Note 4

1

mVrms

Responsivity

16

22

28

V/

SE

Saturation exposure

See Note 5

155

Analog output saturation voltage

2.5

3.4

V

DSNU

Dark signal nonuniformity

All pixels

See Note 6

25

120

mV

IL

Image lag

See Note 7

0.5%

Supply current, output idle

53

80

mA

High-level input current

10

μA

Low-level input current

10

μA

V

High level output voltage SO1 and SO2

4.5

4.95

V

High-level output voltage, SO1 and SO2

4.6

V

V

Low level output voltage SO1 and SO2

0.01

0.1

V

Low-level output voltage, SO1 and SO2

0.4

V

Input capacitance, SI

35

pF

70

pF

NOTES: 1. The array is uniformly illuminated with a diffused LED source having a peak wavelength of 640 nm.

2. PRNU is the maximum difference between the voltage from any single pixel and the average output voltage from all pixels of the

device under test when the array is uniformly illuminated at the white irradiance level. PRNU includes DSNU.

3. Nonlinearity is defined as the maximum deviation from a best-fit straight line over the dark-to-white irradiance levels, as a percent

of analog output voltage (white).

4. RMS noise is the standard deviation of a single-pixel output under constant illumination as observed over a 5-second period.

6. DSNU is the difference between the maximum and minimum output voltage in the absence of illumination.

7. Image lag is a residual signal left in a pixel from a previous exposure. It is defined as a percent of white-level signal remaining after

a pixel is exposed to a white condition followed by a dark condition:

IL +

Vout (IL) * Vdrk

Vout (white) * Vdrk

100

Timing Requirements (see Figure 1 and Figure 2)

MIN

NOM

MAX

UNIT

Setup time, serial input (see Note 8)

20

ns

Hold time, serial input (see Note 8 and Note 9)

0

ns

Pulse duration, clock high or low

50

ns

Input transition (rise and fall) time

0

500

ns

9. SI must go low before the rising edge of the next clock pulse.