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S3031 Datasheet(PDF) 7 Page - Applied Micro Circuits Corporation |
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S3031 Datasheet(HTML) 7 Page - Applied Micro Circuits Corporation |
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7 / 26 page  E4/STM-1/OC-3 ATM TRANSCEIVER S3031B 7 August 19, 1999 / Revision D S3031B RECEIVER OPERATION The S3031B transceiver chip provides the first stage of the digital process of a receive SONET STS-3 or ITU- T E4 serial bit stream. A Coded Mark Inversion (CMI) decoder can be enabled for decoding STS-3 electrical and E4 signal. The recovered and decoded signal is output as both retimed bit-serial 155.52 or 139.264 Mbps NRZ data and as a 38.88 or 34.816 Mbyte/s 4-bit nibble parallel outputs. Clock recovery is performed on the incoming scrambled NRZ or CMI-coded data stream. A reference clock is required for phase locked loop start-up and proper operation under loss of signal conditions. An integral prescaler and phase locked loop circuit is used to multiply this reference frequency to the nominal bit rate. Clock Recovery The clock recovery function, as shown in the block diagram in Figure 9, generates a clock that is fre- quency matched to the incoming data baud rate at the RSDATIP/N differential inputs. The clock is phase aligned by a PLL so that it samples the data in the center of the data eye pattern. The phase relationship between the edge transitions of the data and those of the generated clock are compared by a phase/frequency discriminator. Out- put pulses from the discriminator indicate the required direction of phase corrections. These pulses are smoothed by an integral loop filter. The output of the loop filter controls the frequency of the Voltage Con- trolled Oscillator (VCO), which generates the recov- ered clock. Frequency stability without incoming data is guaranteed by an alternate reference input (REFCLK) to which the PLL locks when data is lost. When the Test Clock Enable (TSTCLKEN) input is set high, the clock recovery block is disabled. The Test Clock (TESTCLK) is used as the bit rate clock input in place of the recovered clock. This feature is used for functional testing of the device. The loop filter transfer function is optimized to enable the PLL to track the jitter, yet tolerate the minimum transition density expected in a received SONET or E4 data signal. This transfer function yields a typical capture time of 16 µs for random incoming NRZ data. The total loop dynamics of the clock recovery PLL yield a jitter tolerance which exceeds the minimum tolerance proposed for OC-3/STM-1/E4 equipment by the Bellcore and ITU-T documents, shown in Figure 12. Optical and Electrical Interfaces The digital data inputs (RSDATIP/N) are the PECL inputs from an optical to electrical converter, as shown in Figure 16. The data input for the coaxial interface is ANDATIN, which is the serial data input from the equal- izer circuit and should be connected as shown in Figure 19. The EQUALSEL input is used to select either RSDATIP/N or ANDATIN. CMI Decoding The CMI decoder block on the S3031B accepts serial data from the TSDATIP/N input at the rate of 139.264 or 155.52 Mbps. The incoming CMI data, which has tran- sitions that represent this data rate (the clock associ- ated with this data would be running at twice this rate), is then decoded from CMI to NRZ format. Loss of Signal The clock recovery circuit monitors the incoming data stream for loss of signal. If the incoming encoded data stream has had no transitions continuously for 100 to 200 recovered clock cycles, loss of signal is declared and the PLL will switch from locking onto the incoming data to locking onto the reference clock per the require- ments of G.775. Alternatively, the loss-of signal (LOSIN) input can force a loss-of-signal condition. This signal is compared internally against the LOSREF input refer- ence voltage. This input can be set to meet the condi- tions shown in Figure 10. If the zero to peak signal level drops below the LOSREF/20 voltage level for more than 100 to 200 bit intervals, a loss of signal condition will be indicated on the LOSOUT pin and the PLL will change its reference from the serial data stream to the reference clock. When the peak input voltage is greater than LOSREF/10, the loss of signal condition will be deasserted and the PLL will recover the clock from the serial data inputs. In clock recovery mode, the receiver PLL also moni- tors the reference clock with respect to the VCO. If the VCO drifts away from the local reference clock by more than 1000 ppm the PLL will re-lock to the refer- ence clock and the LOSOUT will be set to the active low condition. The LOSOUT will return to the High or inactive state and the PLL will again lock to the data if the serial data contains sufficient transition density (less than 100 to 200 bit times between rising edges), and the serial clock is within 250 ppm of the reference clock deter- mined frequency. |
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