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AFBR-5978Z Datasheet(PDF) 6 Page - AVAGO TECHNOLOGIES LIMITED |
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AFBR-5978Z Datasheet(HTML) 6 Page - AVAGO TECHNOLOGIES LIMITED |
6 / 14 page 6 Table 1. Transceiver soft diagnostics Timing characteristics Parameter Symbol Min Max Unit Notes Hardware TX_DISABLE assert time t_off 10 µs Note 1, Figure 6 Hardware TX_DISABLE negate time t_on 1 ms Note 2, Figure 6 Time to initialize t_init 100 ms Note 3, Figure 6 Hardware RX_SD assert time t_sd_on 100 µs Note 4 Hardware RX_SD de-assert time t_sd_off 100 µs Note 5 Software TX_DISABLE assert time t_off_soft 100 ms Note 6 Software TX_DISABLE negate time t_on_soft 100 ms Note 7 Software RX_SD assert time t_sd_on_soft 100 ms Note 8 Software RX_SD de-assert time t_sd_off_soft 100 ms Note 9 Analog parameter data ready t_data 1000 ms Note 10 Serial bus hardware ready t_serial 300 ms Note 11 Write cycle time t_write 10 ms Note 12 Serial ID clock rate f_serial_clock 400 kHz Note 13 Notes: 1. Time from rising edge of TX_DISABLE to when the optical output falls below 10% of nominal. 2. Time from falling edge of TX_DISABLE to when the modulated optical output rises above 90% of nominal. 3. Time from Power on or falling edge of TX_DISABLE to when the modulated optical output rises above 90% of nominal. 4. Time from valid optical signal to RX_SD assertion. 5. Time from loss of optical signal to RX_SD de-assertion. 6. Time from two-wire interface assertion of TX_DISABLE (A2h, byte 110, bit 6) to when the optical output falls below 10% of nominal. Measured from falling clock edge after stop bit of write transaction. 7. Time from two-wire interface de-assertion of TX_DISABLE (A2h, byte110, bit 6) to when the modulated optical output rises above 90% of nominal. 8. Time for two-wire interface assertion of RX_SD (A2h, byte 110, bit 1) from presence of valid optical signal. 9. Time for two-wire interface de-assertion of RX_SD (A2h, byte 110, bit 1) from loss of optical signal. 10. From power on to data ready bit asserted (A2h, byte 110, bit 0). Data ready indicates analog monitoring circuitry is operational. 11. Time from power on until module is ready for data transmission over the serial bus (reads or writes over A0h and A2h). 12. Time from stop bit to completion of a 1-8 byte write command. 13. Contact Avago Technologies for applications at faster (>400 kHz) Serial ID clock rates. |
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