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ADJD-S312-CR999 Datasheet(PDF) 10 Page - AVAGO TECHNOLOGIES LIMITED |
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ADJD-S312-CR999 Datasheet(HTML) 10 Page - AVAGO TECHNOLOGIES LIMITED |
10 / 18 page 10 Figure 4: Data Byte Transfer Figure 5: Slave-Receiver Acknowledge Figure 6: Master-Receiver Acknowledge SDA SCL MSB LSB 1 2 8 9 ACK 1 2 8 9 NO ACK S or Sr Sr or P P Sr START or repeated START condition STOP or repeated START condition MSB LSB A complete data transfer is 8-bits long or 1-byte. Each byte is sent most significant bit (MSB) first followed by an acknowledge or not acknowledge bit. Each data transfer can send an unlimited number of bytes (depending on the data format). See Figure 4. Acknowledge/Not acknowledge The receiver must always acknowledge each byte sent in a data transfer. In the case of the slave-receiver and master-transmitter, if the slave-receiver does not send an acknowledge bit, the master-transmitter can either STOP SCL (MASTER) 8 9 SDA (SLAVE-RECEIVER) SDA (MASTER-TRANSMITTER) LSB Acknowledge Acknowledge clock pulse SDA left HIGH by transmitter SDA pulled LOW by receiver SCL (MASTER) 8 9 SDA (SLAVE-TRANSMITTER) SDA (MASTER-RECEIVER) Acknowledge clock pulse LSB SDA left HIGH by transmitter Not acknowledge SDA left HIGH by receiver P Sr STOP or repeated START condition the transfer or generate a repeated START to start a new transfer. See Figure 5. In the case of the master-receiver and slave-transmitter, the master generates a not acknowledge to signal the end of the data transfer to the slave-transmitter. The mas- ter can then send a STOP or repeated START condition to begin a new data transfer. In all cases, the master generates the acknowledge or not acknowledge SCL clock pulse. See Figure 6. |
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