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ADNV-6340 Datasheet(PDF) 6 Page - AVAGO TECHNOLOGIES LIMITED |
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ADNV-6340 Datasheet(HTML) 6 Page - AVAGO TECHNOLOGIES LIMITED |
6 / 52 page 6 Laser Bin Table Bin Number Rbin Resistor Value (kohm) Match_Bit (Reg 0x2C, Bit7) 2A 18.7 0 3A 12.7 0 Notes (for Figure 5) · Caps for pins 11, 12, 16 and 18 MUST have trace lengths LESS than 5 mm on each side. · Pins 16 and 18 caps MUST use pin 17 GND. · Pin 9, if used, should not be connected to PCB GND to reduce po- tential RF emissions. · The 0.1 uF caps must be ceramic. · Caps should have less than 5 nH of self inductance. · Caps should have less than 0.2 W ESR. · NC pins should not be connected to any traces. · Surface mount parts are recommended. · Care must be taken when interfacing a 5V microcontroller to the ADNS-6010. Serial port inputs on the sensor should be con- nected to open-drain outputs from the microcontroller or use an active drive level shifter. NPD and RESET should be connected to 5V microcontroller outputs through a resistor divider or other level shifting technique. · VDD3 and GND should have low impedance connections to the power supply. · Because the RBIN pin sets the XY_LASER current, the following PC board layout practices should be followed to reduce the chance of uncontrolled laser drive current caused from a leakage path between RBIN and ground. One hypothetical source of such a leakage path is PC board contamination due to a liquid, such as a soft drink, being deposited on the printed circuit board. o The RBIN resistor should be located close to the sensor pin 13. The traces between the resistor and the sensor should be short. o The pin 13 solder pad and all exposed conductors connected to pin 13 should be surrounded by a guard trace connected to VDD3 and devoid of a solder mask. o The pin 13 solder pad, the traces connected to pin 13, and the RBIN resistor should be covered with a conformal coating. o The RBIN resistor should be a thru-hole style to increase the dis- tance between its terminals. This does not apply if a conformal coating is used. LASER Drive Mode The LASER has 2 modes of operation: DC and Shutter. In DC mode, the LASER is on at all times the chip is powered except when in the power down mode via the NPD pin. In shutter mode the LASER is on only during the portion of the frame that light is required. The LASER mode is set by the LASER_MODE bit in the Configuration_bits regis- ter. For optimum product lifetime, Avago Technologies recommends the default Shutter mode setting (except for calibration and test). Eye Safety The ADNS-6010 and the associated components in the schematic of Figure 5 are intended to comply with Class 1 Eye Safety Requirements of IEC 60825-1. Avago Tech- nologies suggests that manufacturers perform testing to verify eye safety on each mouse. It is also recommended to review possible single fault mechanisms beyond those described below in the section “Single Fault Detection”. Under normal conditions, the ADNS-6010 generates the drive current for the laser diode (ADNV-6340). In order to stay below the Class 1 power requirements, resistor Rbin must be set at least as high as the value in the bin table of Figure 5, based on the bin number of the laser diode and LP_CFG0 and LP_CFG1 must be programmed to appropriate values. Avago Technologies recommends using the exact Rbin value specified in the bin table to ensure sufficient laser power for navigation. The sys- tem comprised of the ADNS-6010 and ADNV-6340 is designed to maintain the output beam power within Class 1 requirements over component manufacturing tolerances and the recommended temperature range when adjusted per the procedure below and when implemented as shown in the recommended application circuit of Figure 5. For more information, please refer to Avago Technologies ADNB-6001, ADNB-6002, ADNB- 6011 and ADNB-6012 Laser Mouse Eye Safety Calculation Application Note 5088. LASER Power Adjustment Procedure 1. The ambient temperature should be 25C +/- 5C. 2. Set VDD3 to its permanent value. 3. Ensure that the laser drive is at 100% duty cycle. 4. Program the LP_CFG0 and LP_CFG1 registers to achieve an output power as close to 506uW as pos- sible without exceeding it. Good engineering practices should be used to guaran- tee performance, reliability and safety for the product design. Avago Technologies has additional information and detail, such as firmware practices, PCB layout sugges- tions, and manufacturing procedures and specifications that could be provided. |
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