KK74ACT74D datasheet(4/6 Pages) KODENSHI

Part #	KK74ACT74D

Description	Dual D Flip-Flop with Set and Reset High-Speed Silicon-Gate CMOS

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Manufacturer	KODENSHI [KODENSHI_AUK CORP.]

Direct Link	http://www.kodenshi.co.kr

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KK74ACT74

AC ELECTRICAL CHARACTERISTICS (VCC=5.0 V ± 10%, CL=50pF,Input tr=tf=3.0 ns)

Guaranteed Limits

Symbol

Parameter

25

°C

-40

°C to 85°C

Unit

Min

Max

Min

Max

fmax

Maximum Clock Frequency (Figure 1)

145

125

MHz

tPLH

Propagation Delay, Clock to Q or Q

(Figure 1)

4.0

11.0

4.0

13.0

ns

tPHL

Propagation Delay, Clock to Q or Q

(Figure 1)

3.5

10.0

3.0

11.5

ns

tPLH

Propagation Delay, Set or Reset to Q or Q

(Figure 2)

3.0

9.5

2.5

10.5

ns

tPHL

Propagation Delay, Set or Reset to Q or Q

(Figure 2)

3.0

10.0

3.0

11.5

ns

CIN

Maximum Input Capacitance

4.5

pF

Typical @25

°C,V

CC=5.0 V

CPD

Power Dissipation Capacitance

35

pF

TIMING REQUIREMENTS (VCC=5.0 V ± 10%, CL=50pF, Input tr=tf=3.0 ns)

Guaranteed Limits

Symbol

Parameter

25

°C

-40

°C to

85

°C

Unit

tsu

Minimum Setup Time, Data to Clock (Figure 3)

3.0

3.5

ns

th

Minimum Hold Time, Clock to Data (Figure 3)

1.0

ns

tw

Minimum Pulse Width, Clock, Set or Reset (Figures

1,2)

5.0

6.0

ns

trec

Minimum Recovery Time, Set or Reset to Clock

(Figure 2)

0

ns

4

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KK74ACT74D Datasheet(PDF) 4 Page - KODENSHI_AUK CORP.

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