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HCTL-2020 Datasheet(PDF) 5 Page - AVAGO TECHNOLOGIES LIMITED |
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HCTL-2020 Datasheet(HTML) 5 Page - AVAGO TECHNOLOGIES LIMITED |
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5 / 19 page  5 Switching Characteristics Table 5. Switching Characteristics Min/Max specifications at VDD = 5.0 ± 5%, TA = -40 to + 85°C. Symbol Description Min. Max. Units 1tCLK Clock period 70 ns 2tCHH Pulse width, clock high 28 ns 3tCD[1] Delay time, rising edge of clock to valid, updated count 65 ns information on D0-7 4tODE Delay time, OE fall to valid data 65 ns 5tODZ Delay time, OE rise to Hi-Z state on D0-7 40 ns 6tSDV Delay time, SEL valid to stable, selected data byte 65 ns (delay to High Byte = delay to Low Byte) 7tCLH Pulse width, clock low 28 ns 8tSS[2] Setup time, SEL before clock fall 20 ns 9tOS[2] Setup time, OE before clock fall 20 ns 10 tSH[2] Hold time, SEL after clock fall 0 ns 11 tOH[2] Hold time, OE after clock fall 0 ns 12 tRST Pulse width, RST low 28 ns 13 tDCD Hold time, last position count stable on D0-7 after clock rise 10 ns 14 tDSD Hold time, last data byte stable after next SEL state change 5 ns 15 tDOD Hold time, data byte stable after OE rise 5 ns 16 tUDD Delay time, U/D valid after clock rise 45 ns 17 tCHD Delay time, CNTDCDR or CNTCAS high after clock rise 45 ns 18 tCLD Delay time, CNTDCDR or CNTCAS low after clock fall 45 ns 19 tUDH Hold time, U/D stable after clock rise 10 ns 20 tUDCS Setup time, U/D valid before CNTDCDR or CNTCAS rise tCLK-45 ns 21 tUDCH Hold time, U/D stable after CNTDCDR or CNTCAS rise tCLK-45 ns Notes: 1. tCD specification and waveform assume latch not inhibited. 2. tSS, tOS, tSH, tOH only pertain to proper operation of the inhibit logic. In other cases, such as 8 bit read operations, these setup and hold times do not need to be observed. Figure 3. Tri-State Output Timing. |
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