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TAS3204PAGR Datasheet(PDF) 9 Page - Texas Instruments |
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TAS3204PAGR Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 72 page  www.ti.com TAS3204 AUDIO DSP WITH ANALOG INTERFACE SLES197 – APRIL 2007 TERMINAL INPUT/ PULLUP/ DESCRIPTION OUTPUT(1) PULLDOWN(2) NAME NO. I2C1_SDA 2 Digital I/O Slave I2C serial clock input. Normally connected to system micro. Master I2C serial control data interface input/output. Normally I2C2_SCL 64 Digital Input connected to EEPROM. I2C2_SDA 63 Digital I/O Master I2C serial clock input. Normally connected to EEPROM. LRCLK_IN 58 Digital Input Pulldown Serial data input left/right clock for I2S interface LRCLK_OUT 51 Digital Output Serial data output left/right clock for I2S interface MCLK input is used in slave mode. MCLK_IN must be locked to MCLK_IN 43 Digital Input Pulldown LRCLK_IN, and the frequency is 512Fs (24.576 MHz for 48-kHz Fs). MCLK_OUT1 48 Digital Output 12.288 MHz clock output. This output is valid even when reset is LOW. The frequency for this clock is 6.144 MHz/(n+1) where n is programable MCLK_OUT2 47 Digital Output in the range 0 to 255. Default value is 1.024 MHz. This output is valid even when reset is LOW. The frequency for this clock is 512 kHz/(n+1) where n is programmable MCLK_OUT3 46 Digital Output in the range 0 to 255. Default value is 512 kHz. This output is valid even when reset is LOW. This pin needs to be programmed as mute pin in the application code. MUTE 5 Digital Input Pulldown In has no function in default after reset. Power down, active LOW. After successful boot, its function is defined PDN 7 Digital Input by the boot code. RESERVED 50 N/A Pulldown Connect to ground. System reset input, active low. A system reset is generated by applying RESET 62 Digital Input Pullup a logic LOW to this terminal. Requires a 22-k Ω (1%) external resistor to ground to set analog REXT 27 Analog Output currents. Trace capacitance must be kept low. SCLK_IN 59 Digital Input Serial data input bit clock for I2S interface SCLK_OUT 52 Digital Output Serial data output bit clock for I2S interface SDIN1/GPIO3 61 Digital I/O Pullup Serial data input #1 for I2S interface or programmable for GPIO #3 SDIN2/GPIO4 60 Digital I/O Pullup Serial data input #2 for I2S interface or programmable for GPIO #4 SDOUT1 54 Digital Output Serial data output #1 for I2S interface SDOUT2 53 Digital Output Serial data output #2 for I2S interface Analog mid supply reference. This pin must be decoupled with a 0.1- µF VMID 25 Analog Output low-ESR capacitor and an external 10- µF filter cap.(4) Voltage reference for analog supply. A pin-out of the internally regulated 1.8 V power. A 0.1- µF low ESR capacitor and a 4.7-µF filter VR_ANA 39 Power capacitor must be connected between this terminal and AVSS_PLL. This terminal must not be used to power external devices.(4) Voltage reference for digital supply. A pin-out of the internally regulated 1.8 V power. A 0.1- µF low ESR capacitor and a 4.7-µF filter capacitor VR_DIG 55 Power must be connected between this terminal and DVSS. This terminal must not be used to power external devices.(4) Voltage reference for DPLL supply. A pin-out of internally regulated 1.8-V power supply. A 0.1- µF low-ESR capacitor and a 4.7-µF filter VR_PLL 10 Power capacitor must be connected between this terminal and DVSS. This terminal must not be used to power external devices.(4) Band gap output. A 0.1- µF low ESR capacitor should be connected VREF 26 Analog Output between this terminal and AVSS_PLL. This terminal must not be used to power external devices.(4) Voltage regulator enable. When enabled LOW, this input causes the VREG_EN 49 Digital Input power-supply regulators to be enabled. XTAL_IN 41 Digital Input Crystal input. A 24.576-MHz (512Fs) crystal should be used. XTAL_OUT 42 Digital Output Crystal output. (4) If desired, low ESR capacitance values can be implemented by paralleling two or more ceramic capacitors of equal value. Paralleling capacitors of equal value provide an extended high frequency supply decoupling. Submit Documentation Feedback Physical Characteristics 9 |
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