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FM25C160-GA Datasheet(PDF) 8 Page - Ramtron International Corporation |
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FM25C160-GA Datasheet(HTML) 8 Page - Ramtron International Corporation |
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8 / 13 page  FM25C160 - Automotive Temp. Rev. 3.1 July 2007 Page 8 of 13 Figure 9. Memory Write Figure 10. Memory Read Endurance Internally, a FRAM operates with a read and restore mechanism similar to a DRAM. Therefore, endurance cycles are applied for each access: read or write. The FRAM architecture is based on an array of rows and columns. Each access causes an endurance cycle for an entire row. Therefore, data locations targeted for substantially differing numbers of cycles should not be located within the same row. In the FM25C160, there are 512 rows each 32 bits wide. Regardless, FRAM read and write endurance is effectively unlimited at the 15 MHz clock speed. Even at 2000 accesses per second to the same row, 15 years time will elapse before 10 12 endurance cycles occur. |
Similar Part No. - FM25C160-GA |
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Similar Description - FM25C160-GA |
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