MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>

PS21204

TRANSFER-MOLD TYPE

INSULATED TYPE

Aug. 1999

Fig. 8 TYPICAL DIP-IPM APPLICATION CIRCUIT EXAMPLE

Note 1 : To prevent the input signals oscillation, an RC coupling at each input is recommended, and the wiring of each input should be as short

as possible. (Less than 2cm)

2: By virtue of integrating an application specific type HVIC inside the module, direct coupling to CPU terminals without any opto-coupler

or transformer isolation is possible.

5.1k

Ω resistance.

= 22 nF

5: Each input signal line should be pulled up to the 5V power supply with approximately 4.7k

Ω resistance (other RC coupling circuits at

each input may be needed depending on the PWM control scheme used and on the wiring impedances of the system’s printed circuit

board). Approximately a 0.22~2

µF by-pass capacitor should be used across each power supply connection terminals.

6: To prevent errors of the protection function, the wiring of A, B, C should be as short as possible.

µs.

8: Each capacitor should be put as nearby the pins of the DIP-IPM as possible.

9: To prevent surge destruction, the wiring between the smoothing capacitor and the P&N1 pins should be as short as possible. Approxi-

mately a 0.1~0.22

µF snubber capacitor between the P&N1 pins is recommended.

HO

HO

DIP-IPM

C1: Tight to lerance temp-compensated electrolytic type; C2,C3: 0.22~2

µ F R-category ceramic capacitor for noise filtering

(Note : The capacitance value depends on the PWM control used in the applied system)

C3

C3

C3

C3

C2

C2

C2

C1

C1

C1

HO

IN

IN

15V line

5V line

5V line

IN

COM

COM

COM

CFO

GND

F

o

C

B

A

CFO

R1

C5

Shunt

Resistor

CIN

CIN

N1

N

W

V

U

P

Fo

M

For detailed description of the boot-strap circuit

construction, please contact Mitsubishi Electric

C

P

U

U

N

I

T