3

Low Level Output Voltage

0.05

1.5

-

0.1

-

0.1

-

0.1

V

0.05

3

-

0.1

-

0.1

-

0.1

V

0.05

4.5

-

0.1

-

0.1

-

0.1

V

12

3

-

0.36

-

0.44

-

0.5

V

24

4.5

-

0.36

-

0.44

-

0.5

V

75

(Note 6, 7)

5.5

-

-

-

1.65

-

-

V

50

(Note 6, 7)

5.5

-----

1.65

V

Input Leakage Current

GND

-

5.5

-

±0.1

-

±1-

±1

µA

Quiescent Supply Current

SSI

GND

0

5.5

-

4

-

40

-

80

µA

ACT TYPES

High Level Input Voltage

-

-

4.5 to

5.5

2-2-2-

V

Low Level Input Voltage

-

-

4.5 to

5.5

-

0.8

-

0.8

-

0.8

V

High Level Output Voltage

-0.05

4.5

4.4

-

4.4

-

4.4

-

V

-24

4.5

3.94

-

3.8

-

3.7

-

V

-75

(Note 6, 7)

5.5

-

-

3.85

-

-

-

V

-50

(Note 6, 7)

5.5

----

3.85

-

V

Low Level Output Voltage

0.05

4.5

-

0.1

-

0.1

-

0.1

V

24

4.5

-

0.36

-

0.44

-

0.5

V

75

(Note 6, 7)

5.5

-

-

-

1.65

-

-

V

50

(Note 6, 7)

5.5

-----

1.65

V

Input Leakage Current

GND

-

5.5

-

±0.1

-

±1-

±1

µA

Quiescent Supply Current

SSI

GND

0

5.5

-

4

-

40

-

80

µA

Additional Supply Current per

Input Pin TTL Inputs High

1 Unit Load

-2.1

-

4.5 to

5.5

-

2.4

-

2.8

-

3

mA

NOTES:

17. Test one output at a time for a 1-second maximum duration. Measurement is made by forcing current and measuring voltage to minimize

power dissipation.

18. Test verifies a minimum 50

ACT Input Load Table

INPUT

UNIT LOAD

All

0.32

NOTE: Unit load is

PARAMETER

SYMBOL

TEST

CONDITIONS

(V)

UNITS

MIN

MAX

MIN

MAX

MIN

MAX

CD74AC02, CD74ACT02