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PPC405EX-SPAFFFTX Datasheet(PDF) 6 Page - Applied Micro Circuits Corporation |
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PPC405EX-SPAFFFTX Datasheet(HTML) 6 Page - Applied Micro Circuits Corporation |
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6 / 67 page  PPC405EX – PowerPC 405EX Embedded Processor 6 AMCC Proprietary Revision 1.09 - August 21, 2007 Preliminary Data Sheet Address Maps The PPC405EX incorporates two address maps. The first address map defines the possible use of addressable memory regions that the processor can access. The second address map defines Device Configuration Register (DCR) addresses (numbers). The DCRs are accessed by software running on the PPC405EX processor through the use of mtdcr and mfdcr instructions. Table 1. System Memory Address Map (4GB System Memory) Function Subfunction Start Address (Hex) End Address (Hex) Size Local Memory DDR 1/2 SDRAM 0 0000 0000 0 7FFF FFFF 2GB EBC 0 8000 0000 0 8FFF FFFF 256MB PCI Express 0 9000 0000 0 EF5F 00FF 1.5GB OPB Peripherals GPT 0 EF60 0000 0 EF60 01FF 512B UART 0 0 EF60 0200 0 EF60 0207 8B Reserved 0 EF60 0208 0 EF60 02FF 248B UART 1 0 EF60 0300 0 EF60 0307 8B Reserved 0 EF60 0308 0 EF60 03FF 248B IIC 0 0 EF60 0400 0 EF60 041F 32B Reserved 0 EF60 0420 0 EF60 04FF 224B IIC 1 0 EF60 0500 0 EF60 051F 32B Reserved 0 EF60 0520 0 EF60 05FF 224B SCP 0 EF60 0600 0 EF60 0605 6B Reserved 0 EF60 0606 0 EF60 06FF 250B OPB Arbiter 0 EF60 0700 0 EF60 073F 64B Reserved 0 EF60 0740 0 EF60 07FF 192B GPIO 0 EF60 0800 0 EF60 087F 128B Reserved 0 EF60 0880 0 EF60 08FF 128B Ethernet 0 0 EF60 0900 0 EF60 09FF 256B Ethernet 1 0 EF60 0A00 0 EF60 0AFF 256B RGMII Bridge 0 EF60 0B00 0 EF60 0C03 260B Reserved 0 EF60 0C04 0 EF60 FFFF 62KB PLB/AHB Peripherals PKA +TRNG 0 EF61 0000 0 EF61 FFFF 64KB PCI Express Interrupt Handler 0 EF62 0000 0 EF62 00FF 256B Reserved 0 EF62 0100 0 EF6B FFFF 640KB USB OTG 0 EF6C 0000 0 EF6F FFFF 256KB Security 0 EF70 0000 0 EF77 FFFF 512KB Reserved 0 EF78 0000 0 EFFF FFFF 8.9MB EBC EBC Memory 0 F000 0000 0 FFDF FFFF 254MB EBC Memory—Boot ROM 0 FFE0 0000 0 FFFF FFFF 2MB Notes: 1. If peripheral bus boot is selected, peripheral bank 0 is automatically configured at reset to the address range listed above. 2. After the boot process, software may reassign the boot memory regions for other uses. 3. PCI Express can use PLB address range 1 0000 0000 to FFFF FFFF FFFF FFFF even though the CPU can not access it. |
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