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STARTING A CONVERSION

ADS8505

SLAS180B – SEPTEMBER 2005 – REVISED JUNE 2007

BASIC OPERATION (continued)

The ADS8505 begins tracking the input signal at the end of the conversion. Allowing 4

µs between convert

commands assures accurate acquisition of a new signal.

The offset and gain are adjusted internally to allow external trimming with a single supply. The external resistors

compensate for this adjustment and can be left out if the offset and gain are corrected in software (refer to the

CALIBRATION section).

The combination of CS (pin 25) and R/C (pin 24) low for a minimum of 40 ns immediately puts the sample/hold

of the ADS8505 in the hold state and starts conversion n. BUSY (pin 26) goes low and stays low until

conversion n is completed and the internal output register has been updated. All new convert commands during

BUSY low will abort the conversion in progress and reset the ADC (see Figure 26).

The ADS8505 begins tracking the input signal at the end of the conversion. Allowing 4

µs between convert

commands assures accurate acquisition of a new signal. Refer to Table 1 for a summary of CS, R/C, and BUSY

states and Figure 23 through Figure 25 for the timing diagrams.

CS and R/C are internally ORed and level triggered. There is not a requirement which input goes low first when

initiating a conversion. If, however, it is critical that CS or R/C initiates conversion n, be sure the less critical

input is low at least 10 ns prior to the initiating input.

To reduce the number of control pins, CS can be tied low using R/C to control the read and convert modes. The

parallel output becomes active whenever R/C goes high. Refer to the READING DATA section.

Table 1. Control Line Functions for Read and Convert

CS

R/C

BUSY

OPERATION

1

X

X

None. Databus is in Hi-Z state.

↓

0

1

Initiates conversion n. Databus remains in Hi-Z state.

0

↓

1

Initiates conversion n. Databus enters Hi-Z state.

0

1

↑

Conversion n completed. Valid data from conversion n on the databus.

↓

1

1

Enables databus with valid data from conversion n.

↓

1

0

0

↑

0

0

0

↑

Data is invalid. CS and/or R/C must be high when BUSY goes high.

X

↓

0

(1)

See Figure 23 and Figure 24 for constraints on data valid from conversion n-1.

(2)

See Figure 26 for details on ADC reset.

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