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405GPR Datasheet(PDF) 10 Page - Applied Micro Circuits Corporation |
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405GPR Datasheet(HTML) 10 Page - Applied Micro Circuits Corporation |
10 / 57 page 405GPr – Power PC 405GPr Embedded Processor 10 AMCC Revision 2.04 – September 7, 2007 Data Sheet • Supports PCI target access to all PLB address spaces • Supports PowerPC processor boot from PCI memory SDRAM Memory Controller The PPC405GPr Memory Controller core provides a low latency access path to SDRAM memory. A variety of system memory configurations are supported. The memory controller supports up to four physical banks. Up to 256MB per bank are supported, up to a maximum of 1GB. Memory timings, address and bank sizes, and memory addressing modes are programmable. Features include: • 11x8 to 13x11 addressing for SDRAM (2- and 4-bank) • 32-bit memory interface support • Programmable address compare for each bank of memory • Industry standard 168-pin DIMMS are supported (some configurations) • PC-133 support for 133 MHz memory • 4MB to 256MB per bank • Programmable address mapping and timing • Auto refresh • Page mode accesses with up to 4 open pages • Power management (self-refresh) • Error checking and correction (ECC) support - Standard single-error correct, double-error detect coverage - Aligned nibble error detect - Address error logging External Peripheral Bus Controller (EBC) • Supports eight banks of ROM, EPROM, SRAM, Flash memory, or slave peripherals • Up to 66MHz operation • Burst and non-burst devices • 8-, 16-, 32-bit byte-addressable data bus width support • Latch data on Ready • Programmable 2K clock time-out counter with disable for Ready • Programmable access timing per device - 0–255 wait states for non-bursting devices - 0–31 burst wait states for first access and up to 7 wait states for subsequent accesses |
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