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PPC440EP-3PBFFFCX Datasheet(PDF) 1 Page - Applied Micro Circuits Corporation |
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PPC440EP-3PBFFFCX Datasheet(HTML) 1 Page - Applied Micro Circuits Corporation |
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1 / 84 page  Part Number 440EP Revision 1.26 – April 25, 2007 AMCC Proprietary 1 440EP Power PC 440EP Embedded Processor Data Sheet Features •PowerPC® 440 processor core operating up to 667MHz with 32KB I-cache and D-cache with parity checking. • Selectable processor:bus clock ratios of N:1, N:2. • Floating Point Unit with single- and double- precision and single-cycle throughput. • Dual bridged Processor Local Buses (PLBs) with 64- and 128-bit widths. • Double Data Rate (DDR) Synchronous DRAM (SDRAM) interface operating up to 133MHz with ECC. • DMA support for external peripherals, internal UART and memory. • PCI V2.2 interface (3.3V only). Thirty-two bits at up to 66MHz. • Programmable interrupt controller supports interrupts from a variety of sources. • Programmable General Purpose Timers (GPT). • Two Ethernet 10/100Mbps half- or full-duplex interfaces. Operational modes supported are MII, RMII, and SMII with packet reject. • Up to four serial ports (16750 compatible UART). • Two USB ports. One USB 1.1 Host interface with on-chip PHY. One USB 2.0 Device interface, with dedicated DMA, configured as a 1.1 on-chip PHY or a 2.0 UTMI. • External peripheral bus (16-bit data) for up to six devices with external mastering. • Two IIC interfaces (one with boot parameter read capability). • NAND Flash interface. • SPI interface. • General Purpose I/O (GPIO) interface. • JTAG interface for board level testing. • Boot from PCI memory, NOR Flash on the external peripheral bus, or NAND Flash on the NAND Flash interface. • Available in RoHS compliant lead-free package. Description Designed specifically to address high-end embedded applications, the PowerPC 440EP (PPC440EP) provides a high-performance, low- power solution that interfaces to a wide range of peripherals and incorporates on-chip power management features. This chip contains a high-performance RISC processor, a floating point unit, DDR SDRAM controller, PCI bus interface, control for external ROM and peripherals, DMA with scatter-gather support, Ethernet ports, serial ports, IIC interfaces, SPI interface, USB ports, NAND Flash interface, and general purpose I/O. Technology: CMOS Cu-11, 0.13 μm. Package: 35mm, 456-ball standard plastic ball grid array (E-PBGA), with and without lead (RoHS compliant). Typical power (measured): Less than 3W at 533MHz, 2.5W at 400MHz. Supply voltages required: 3.3V, 2.5V, 1.5V. |
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