M12L128324A datasheet(5/47 Pages) ESMT

Part #	M12L128324A

Description	1M x 32 Bit x 4 Banks Synchronous DRAM

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Manufacturer	ESMT [Elite Semiconductor Memory Technology Inc.]

Direct Link	http://www.esmt.com.tw/index.asp

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5 / 47 page

ESMT

M12L128324A

Elite Semiconductor Memory Technology Inc.

Publication Date: Mar. 2006

Revision: 1.2

5/47

NAME

INPUT FUNCTION

DQM0~3

Data Input / Output Mask

Makes data output Hi-Z, tSHZ after the clock and masks the output.

Blocks data input when DQM active.

DQ0 ~ DQ31

Data Input / Output

Data inputs / outputs are multiplexed on the same pins.

VDD / VSS

Power Supply / Ground

Power and ground for the input buffers and the core logic.

VDDQ / VSSQ

Data Output Power / Ground

Isolated power supply and ground for the output buffers to provide

improved noise immunity.

N.C

No Connection

This pin is recommended to be left No Connection on the device.

ABSOLUTE MAXIMUM RATINGS

Parameter

Symbol

Value

Unit

Voltage on any pin relative to VSS

VIN, VOUT

-1.0 ~ 4.6

V

Voltage on VDD supply relative to VSS

VDD, VDDQ

-1.0 ~ 4.6

V

Storage temperature

TSTG

-55 ~ +150

C

°

Power dissipation

PD

1

W

Short circuit current

IOS

50

mA

Note :

Permanent device damage may occur if ABSOLUTE MAXIMUM RATING are exceeded.

Functional operation should be restricted to recommended operating condition.

Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

DC OPERATING CONDITION

Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70 C

°)

Parameter

Symbol

Min

Typ

Max

Unit

Note

Supply voltage

VDD, VDDQ

3.0

3.3

3.6

V

Input logic high voltage

VIH

2.0

3.0

VDD+0.3

V

1

Input logic low voltage

VIL

-0.3

0

0.8

V

2

Output logic high voltage

VOH

2.4

-

V

IOH = -2mA

Output logic low voltage

VOL

-

0.4

V

IOL = 2mA

Input leakage current

IIL

-5

-

5

μ A

3

Output leakage current

IOL

-5

-

5

μ A

4

Note:

1. VIH(max) = 4.6V AC for pulse width

≤ 10ns acceptable.

2. VIL(min) = -1.5V AC for pulse width

≤ 10ns acceptable.

3. Any input 0V

≤ VIN ≤ VDD + 0.3V, all other pins are not under test = 0V.

4. Dout is disabled , 0V

≤ VOUT ≤ VDD.

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