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M12S16161A-7TG Datasheet(PDF) 8 Page - Elite Semiconductor Memory Technology Inc. |
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M12S16161A-7TG Datasheet(HTML) 8 Page - Elite Semiconductor Memory Technology Inc. |
8 / 29 page ESMT M12S16161A Elite Semiconductor Memory Technology Inc. Publication Date : May. 2007 Revision : 1.1 8/29 Mode Register 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 1 JEDEC Standard Test Set (refresh counter test) 11 10 9 8 7 6 5 4 3 2 1 0 x x 1 0 0 LTMODE WT BL Burst Read and Single Write (for Write Through Cache) 11 10 9 8 7 6 5 4 3 2 1 0 1 0 Use in future 11 10 9 8 7 6 5 4 3 2 1 0 x x x 1 1 v v v v v v v Vender Specific 11 10 9 8 7 6 5 4 3 2 1 0 v =Valid 0 0 0 0 0 LTMODE WT BL Mode Register Set x =Don’t care Bit2-0 WT=0 WT=1 000 1 1 001 2 2 010 4 4 011 8 8 100 R R 101 R R 110 R R Burst length 111 Full page R 0 Sequential Wrap type 1 Interleave Bits6-4 CAS Latency 000 R 001 R 010 2 011 3 100 R 101 R 110 R Latency mode 111 R Mode Register Write Timing Remark R : Reserved Mode Register W rite CLOCK CKE CS RAS WE A0-A11 CAS |
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