M13S128168A datasheet(8/49 Pages) ESMT

Part #	M13S128168A

Description	2M x 16 Bit x 4 Banks Double Data Rate SDRAM

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Manufacturer	ESMT [Elite Semiconductor Memory Technology Inc.]

Direct Link	http://www.esmt.com.tw/index.asp

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8 / 49 page

ESMT

M13S128168A

Elite Semiconductor Memory Technology Inc.

Publication Date : Jun. 2007

Revision : 1.8

8/49

AC Timing Parameter & Specifications-continued

-5

-6

Parameter

Symbol

min

max

min

max

Half Clock Period

tHP

tCLmin or tCHmin

-

tCLmin or tCHmin

-

ns

DQ-DQS output hold

time

tQH

tHP-0.45

-

tHP-0.5

-

ns

ACTIVE to PRECHARGE

command

tRAS

40

120Kns

42

120Kns

ns

Row Cycle Time

tRC

60

-

60

-

ns

AUTO REFRESH Row Cycle

Time

tRFC

70

-

72

-

ns

ACTIVE to READ,WRITE

delay

tRCD

18

-

18

-

ns

PRECHARGE command

period

tRP

18

-

18

-

ns

ACTIVE to READ with

AUTOPRECHARGE

command

tRAP

18

120K

18

120K

ns

ACTIVE bank A to ACTIVE

bank B command

tRRD

10

-

12

-

ns

Write recovery time

tWR

2

-

2

-

tCK

Write data in to READ

command delay

tWTR

1

-

1

-

tCK

Col. Address to Col. Address

delay

tCCD

1

-

1

-

tCK

Average periodic refresh

interval

tREFI

-

15.6

-

15.6

us

Write preamble

tWPRE

0.25

-

0.25

-

tCK

Write postamble

tWPST

0.4

0.6

0.4

0.6

tCK

DQS read preamble

tRPRE

0.9

1.1

0.9

1.1

tCK

DQS read postamble

tRPST

0.4

0.6

0.4

0.6

tCK

Clock to DQS write preamble

setup time

tWPRES

0

-

0

-

ns

Load Mode Register /

Extended Mode register

cycle time

tMRD

2

-

1

-

tCK

Exit self refresh to READ

command

tXSRD

200

-

200

-

tCK

Exit self refresh to

non-READ command

tXSNR

75

-

75

-

ns

Autoprecharge write

recovery+Precharge time

tDAL

(tWR/tCK)

+

(tRP/tCK)

(tWR/tCK)

+

(tRP/tCK)

tCK

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M13S128168A Datasheet(PDF) 8 Page - Elite Semiconductor Memory Technology Inc.

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