M13S128168A-7.5AB datasheet(2/49 Pages) ESMT

Part #	M13S128168A-7.5AB

Description	2M x 16 Bit x 4 Banks Double Data Rate SDRAM

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Manufacturer	ESMT [Elite Semiconductor Memory Technology Inc.]

Direct Link	http://www.esmt.com.tw/index.asp

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2 / 49 page

ESMT

M13S128168A

Elite Semiconductor Memory Technology Inc.

Publication Date : Jun. 2007

Revision : 1.8

2/49

DDR SDRAM

2M x 16 Bit x 4 Banks

Double Data Rate SDRAM

Features

JEDEC Standard

Internal pipelined double-data-rate architecture, two data access per clock cycle

Bi-directional data strobe (DQS)

On-chip DLL

Differential clock inputs (CLK and CLK )

DLL aligns DQ and DQS transition with CLK transition

Quad bank operation

CAS Latency : 3

Burst Type : Sequential and Interleave

Burst Length : 2, 4, 8

All inputs except data & DM are sampled at the rising edge of the system clock(CLK)

Data I/O transitions on both edges of data strobe (DQS)

DQS is edge-aligned with data for reads; center-aligned with data for WRITE

Data mask (DM) for write masking only

VDD = 2.375V ~ 2.75V, VDDQ = 2.375V ~ 2.75V

Auto & Self refresh

15.6us refresh interval (64ms refresh period, 4K cycle)

SSTL-2 I/O interface

66pin TSOPII package

Ordering information :

PRODUCT NO.

MAX FREQ

VDD

PACKAGE

COMMENTS

M13S128168A -5TG

200MHz

Pb-free

M13S128168A -6TG

166MHz

2.5V

TSOPII

Pb-free

M13S128168A -5BG

200MHz

Pb-free

M13S128168A -6BG

166MHz

2.5V

BGA

Pb-free

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