M13S128324A-5LG datasheet(6/49 Pages) ESMT

Part #	M13S128324A-5LG

Description	1M x 32 Bit x 4 Banks Double Data Rate SDRAM

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Manufacturer	ESMT [Elite Semiconductor Memory Technology Inc.]

Direct Link	http://www.esmt.com.tw/index.asp

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6 / 49 page

ESMT

M13S128324A

Elite Semiconductor Memory Technology Inc.

Publication Date : May. 2007

Revision : 1.8

6/49

DC Specifications

Version

Unit

Note

Parameter

Symbol

Test Condition

-3.6

-4

-5

-6

-

Operation Current

(One Bank Active)

IDD0

tRC = tRC (min) tCK = tCK (min)

Active – Precharge

235

210

175

145

mA

-

Operation Current

(One Bank Active)

IDD1

Burst Length = 2 tRC = tRC (min),

CL= 2.5 IOUT = 0mA,

Active-Read- Precharge

245

220

190

180

mA

-

Precharge Power-down

Standby Current

IDD2P

CKE

≤ V

IL(max), tCK = tCK (min),

All banks idle

40

mA

-

Idle Standby Current

IDD2N

CKE

≥ V

IH(min),

CS

≥

VIH(min), tCK = tCK (min)

135

120

115

95

mA

-

Active Power-down Standby

Current

IDD3P

All banks ACT, CKE

≤ V

IL(max),

tCK = tCK (min)

60

55

50

45

mA

-

Active Standby Current

IDD3N

One bank; Active-Precharge, tRC

= tRAS(max),

tCK = tCK (min)

150

130

120

110

mA

-

Operation Current (Read)

IDD4R

Burst Length = 2, CL= 2.5 , tCK =

tCK (min), IOUT = 0Ma

440

400

350

300

mA

-

Operation Current (Write)

IDD4W

Burst Length = 2, CL= 2.5 , tCK =

tCK (min)

470

430

380

330

mA

-

Auto Refresh Current

IDD5

tRC ≥ tRFC(min)

320

290

270

250

mA

-

Self Refresh Current

IDD6

CKE

≤ 0.2V

3

mA

1

Note 1. Enable on-chip refresh and address counters.

AC Operation Conditions & Timing Specification

AC Operation Conditions

Parameter

Symbol

Min

Max

Unit

Note

Input High (Logic 1) Voltage, DQ, DQS and DM signals

VIH(AC)

VREF + 0.35

-

V

-

Input Low (Logic 0) Voltage, DQ, DQS and DM signals

VIL(AC)

-

VREF - 0.35

V

-

Input Different Voltage, CLK and CLK inputs

VID(AC)

0.7

VDDQ+0.6

V

1

Input Crossing Point Voltage, CLK and CLK inputs

VIX(AC)

0.5*VDDQ-0.2

0.5*VDDQ+0.2

V

2

Note1. VID is the magnitude of the difference between the input level on CLK and the input on CLK .

2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of

the same.

Input / Output Capacitance

(VDD = 2.375V~2.75V, VDDQ =2.375V~2.75V, TA = 25 C

° , f = 1MHz)

(VDD = 2.5V~2.7V, VDDQ =2.5V~2.7V, TA = 25 C

° , f = 1MHz (for speed -3.6))

(VDD = 2.6V~2.8V, VDDQ =2.6V~2.8V, TA = 25 C

° , f = 1MHz [only for speed -4(CL3)])

Parameter

Symbol

Min

Max

Unit

Input capacitance(A0~A11, BA0~BA1, CKE,

CS , RAS , CAS , WE )

CIN1

1

4

pF

Input capacitance (CLK, CLK )

CIN2

1

5

pF

Data & DQS input/output capacitance

COUT

1

6.5

pF

Input capacitance (DM)

CIN3

1

6.5

pF

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