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CAT25C64LA-1.8-GT3 Datasheet(PDF) 1 Page - Catalyst Semiconductor |
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CAT25C64LA-1.8-GT3 Datasheet(HTML) 1 Page - Catalyst Semiconductor |
1 / 16 page 1 © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT25C64 64K-Bit SPI Serial CMOS EEPROM Doc. No. 1112, Rev. B FEATURES I 10 MHz SPI compatible I 1.8 to 5.5 volt operation I Hardware and software protection I Low power CMOS technology I SPI modes (0,0 &1,1) I Commercial, industrial and automotive temperature ranges I 1,000,000 program/erase cycles I 100 year data tetention I Self-timed write cycle I 8-pin DIP and SOIC I 64-Byte page write buffer I Block write protection – Protect 1/4, 1/2 or all of EEPROM array DESCRIPTION The CAT25C64 is a 64K-Bit SPI Serial CMOS EEPROM internally organized as 8Kx8 bits. Catalyst’s advanced CMOS Technology substantially reduces device power requirements. The CAT25C64 features a 64-byte page write buffer. The device operates via the SPI bus serial interface and is enabled though a Chip Select ( CS). In addition to the Chip Select, the clock input (SCK), data in (SI) and data out (SO) are required to access the device. The HOLD pin may be used to suspend any serial communication without resetting the serial se- quence. The CAT25C64 is designed with software and hardware write protection features including Block write protection. The device is available in 8-pin DIP and SOIC packages. PIN CONFIGURATION PIN FUNCTIONS Pin Name Function SO Serial Data Output SCK Serial Clock WP Write Protect VCC +1.8V to +5.5V Power Supply VSS Ground CS Chip Select SI Serial Data Input HOLD Suspends Serial Input PDIP (P, L) SOIC (S, V) 8 7 6 5 VCC HOLD SCK SI WP CS SO VSS 1 2 3 4 FUNCTIONAL SYMBOL VCC VSS SO SI CS WP HOLD SCK CAT25C64 Not recommended for new designs, replace with CAT25640 |
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