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CAT93C76ZD4I-T3 Datasheet(PDF) 3 Page - Catalyst Semiconductor

Part # CAT93C76ZD4I-T3
Description  8K-Bit Microwire Serial EEPROM
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Manufacturer  CATALYST [Catalyst Semiconductor]
Direct Link  http://www.catalyst-semiconductor.com
Logo CATALYST - Catalyst Semiconductor

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CAT93C76 (Rev. A)
© Catalyst Semiconductor, Inc.
3
Doc. No. MD-1090 Rev. B
Characteristics subject to change without notice
PIN CAPACITANCE
(1)
Symbol
Test
Conditions
Min
Typ
Max
Units
COUT
Output Capacitance (DO)
VOUT = 0V
5
pF
CIN
Input Capacitance (CS, SK, DI, ORG)
VIN = 0V
5
pF
INSTRUCTION SET
(2)
Address
Data
Instruction
Start
Bit
Opcode
x8
x16
x8
x16
Comments
READ
1
10
A10-A0
A9-A0
Read Address AN– A0
ERASE
1
11
A10-A0
A9-A0
Clear Address AN– A0
WRITE
1
01
A10-A0
A9-A0
D7-D0
D15-D0
Write Address AN– A0
EWEN
1
00
11XXXXXXXXX 11XXXXXXXX
Write Enable
EWDS
1
00
00XXXXXXXXX 00XXXXXXXX
Write Disable
ERAL
1
00
10XXXXXXXXX 10XXXXXXXX
Clear All Addresses
WRAL
1
00
01XXXXXXXXX 01XXXXXXXX
D7-D0
D15-D0
Write All Addresses
A.C. CHARACTERISTICS
Limits
VCC = 1.8V - 2.5V
VCC = 2.5V - 5.5V
Symbol
Parameter
Test
Conditions
Min
Max
Min
Max
Units
tCSS
CS Setup Time
100
50
ns
tCSH
CS Hold Time
0
0
ns
tDIS
DI Setup Time
100
50
ns
tDIH
DI Hold Time
100
50
ns
tPD1
Output Delay to 1
250
150
ns
tPD0
Output Delay to 0
CL = 100pF
(3)
250
150
ns
tHZ
(1)
Output Delay to High-Z
150
100
ns
tEW
Program/Erase Pulse Width
5
5
ms
tCSMIN
Minimum CS Low Time
200
150
ns
tSKHI
Minimum SK High Time
250
150
ns
tSKLOW
Minimum SK Low Time
250
150
ns
tSV
Output Delay to Status Valid
250
100
ns
SKMAX
Maximum Clock Frequency
DC
1000
DC
3000
kHz
POWER-UP TIMING
(1)(4)
Symbol
Parameter
Max
Units
tPUR
Power-up to Read Operation
1
ms
tPUW
Power-up to Write Operation
1
ms
Notes:
(1) These parameters are tested initially and after a design or process change that affects the parameter.
(2) Address bit A10 for the 1,024x8 org. and A9 for the 512x16 org. are “don’t care” bits, but must be kept at either a “1” or “0” for READ,
WRITE and ERASE commands.
(3) The input levels and timing reference points are shown in the “AC Test Conditions” table.
(4) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.


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