DG401/403/405

Siliconix

S-53748—Rev. E, 05-Jun-97

7

Schematic Diagram (Typical Channel)

Figure 1.

Level

Shift/

Drive

S

V+

GND

V–

D

V–

V+

Test Circuits

Figure 2.

Switching Time

Figure 3.

Break-Before-Make

0 V

Logic

Input

Switch

Input*

Switch

Output

3 V

0 V

Switch

Input*

the output waveform.

90%

90%

Note: Logic input waveform is inverted for switches that

have the opposite logic sense control

0 V

Logic

Input

Switch

Switch

Output

3 V

50%

0 V

Output

0 V

90%

90%

V+

IN

S

D

–15 V

GND

"10 V

35 pF

V–

1 k

W

+15 V

+5 V

V+

V–

IN

–15 V

GND

+5 V

+15 V

50%