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DG401AK Datasheet(PDF) 7 Page - TEMIC Semiconductors |
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DG401AK Datasheet(HTML) 7 Page - TEMIC Semiconductors |
7 / 10 page DG401/403/405 Siliconix S-53748—Rev. E, 05-Jun-97 7 Schematic Diagram (Typical Channel) Figure 1. Level Shift/ Drive VIN VL S V+ GND V– D V– V+ Test Circuits Figure 2. Switching Time Figure 3. Break-Before-Make 0 V Logic Input Switch Input* Switch Output 3 V 0 V Switch Input* VO is the steady state output with the switch on. Feedthrough via switch capacitance may result in spikes at the leading and trailing edge of the output waveform. VS tr <20 ns tf <20 ns 90% –VS tOFF tON VO 90% VO *VS = 10 V for tON, VS = –10 V for tOFF Note: Logic input waveform is inverted for switches that have the opposite logic sense control 0 V Logic Input Switch Switch Output 3 V 50% 0 V Output 0 V 90% VO2 VO1 90% VS1 VS2 tD tD CL (includes fixture and stray capacitance) V+ IN RL RL + rDS(on) VO = VS S D –15 V VO GND "10 V VL CL 35 pF V– RL 1 k W +15 V +5 V VO2 CL (includes fixture and stray capacitance) V+ RL1 S2 CL1 V– S1 VL VS2 IN D2 VS1 RL2 D1 VO1 CL2 –15 V GND +5 V +15 V 50% |
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