W39V040C

Publication Release Date: Apr. 11, 2006

- 7 -

Revision A1

6.

FUNCTIONAL DESCRIPTION

6.1

Interface Mode Selection and Description

This device can operate in two interface modes, one is Programmer interface mode, and the other is

LPC interface mode. The Mode pin of the device provides the control between these two interface

state (or leaved no connection), it will be in the LPC mode. In Programmer mode, this device just

behaves like traditional flash parts with 8 data lines. But the row and column address inputs are

multiplexed. The row address are mapped to the higher internal address A[18:11]. And the column

address are mapped to the lower internal address A[10:0]. For LPC mode, it complies with the LPC

Interface Specification, through the LAD[3:0] to communicate with the system chipset .

6.2

Read (Write) Mode

In Programmer interface mode, the read (write) operation of the W39V040C is controlled by #OE

(#WE). The #OE (#WE) is held low for the host to obtain (write) data from (to) the outputs (inputs).

#OE is the output control and is used to gate data from the output pins. The data bus is in high

impedance state when #OE is high.

As for in the LPC interface mode, the read or write is determined

by the "START CYCLE ". Refer to the LPC cycle definition and timing waveforms for further details.

6.3

Reset Operation

The #RESET input pin can be used in some application.

When #RESET pin is at high state, the

device is in normal operation mode.

When #RESET pin is at low state, it will halt the device and all

outputs will be at high impedance state.

As the high state re-asserted to the #RESET pin, the device

will return to read or standby mode, it depends on the control signals.

6.4

Accelerated Program Operation

The device provides accelerated program operations through the ACC function.This function is

primarily intended to allow a faster manufacturing throughput in the factory.

6.5

Boot Block Operation and Hardware Protection at Initial- #TBL & #WP

There is a hardware method to protect the top boot block and other sectors. Before power on

programmer, tie the #TBL pin to low state and then the top boot block will not be programmed/erased. If

#WP pin is tied to low state before power on, the other sectors will not be programmed/erased.

In order to detect whether the boot block feature is set on or not, users can perform software command

sequence: enter the product identification mode (see Command Codes for Identification/Boot Block

Lockout Detection for specific code), and then read from address FFF2(hex). You can check the

DQ2/DQ3 at the address FFF2 to see whether the #TBL/#WP pin is in low or high state. If the DQ2 is

“0”, it means the #TBL pin is tied to high state. In such condition, whether boot block can be

programmed/erased or not will depend on software setting. On the other hand, if the DQ2 is “1”, it

means the #TBL pin is tied to low state, then boot block is locked no matter how the software is set.

Like the DQ2, the DQ3 inversely mirrors the #WP state. If the DQ3 is “0”, it means the #WP pin is in

high state, then all the sectors except the boot block can be programmed/erased. On the other hand, if

the DQ3 is “1”, then all the sectors except the boot block are programmed/erased inhibited.To return to

normal operation, perform a three-byte command sequence (or an alternate single-byte command) to

exit the identification mode. For the specific code, see Command Codes for Identification/Boot Block

Lockout Detection.