5

HV219

DATA

IN

LE

CLOCK

DATA

OUT

OFF

ON

OUT

(TYP)

V

50%

50%

50%

50%

50%

50%

50%

CLR

D

N + 1

D

N

D

N - 1

50%

50%

90%

10%

Logic Timing Waveforms

Truth Table

Data in 8-Bit Shift Register

LE

CL

Output Switch State

D0

D1

D2

D3

D4

D5

D6

D7

SW0

SW1

SW2

SW3

SW4

SW5

SW6

SW7

L

L

L

OFF

HL

L

ON

L

L

L

OFF

HL

L

ON

L

L

L

OFF

HL

L

ON

L

L

L

OFF

HL

L

ON

L

L

L

OFF

HL

L

ON

L

L

L

OFF

HL

L

ON

L

L

L

OFF

HL

L

ON

L

L

L

OFF

HL

L

ON

XXXXXXXX

H

L

Hold Previous State

XXXXXXXX

X

H

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

Notes:

1. The eight switches operate independently.

2. Serial data is clocked in on the L to H transition clock.

3. The switches go to a state retaining their present condition at the rising edge of the LE.

4. When LE is low, the shift register data flows through the latch.

5. Shift register clocking has no effect on the switch states if LE is high.

6. The clear input overrides all other inputs.