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SC1405DITSTRT Datasheet(PDF) 7 Page - Semtech Corporation |
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SC1405DITSTRT Datasheet(HTML) 7 Page - Semtech Corporation |
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7 / 14 page  7 2005 Semtech Corp. www.semtech.com SC1405D POWER MANAGEMENT Block Diagram Applications Information SC1405D is designed to drive Low Rds_On power FETs with ultra-low rise/fall times and propagation delays. As the switching frequency of PWM controllers is increased to reduce power supply volume and cost, fast rise and fall times are necessary to minimize switching losses (TOP FET) and reduce Dead-time (BOTTOM FET) losses. While Low Rds_On FETs present a power saving in I2R losses, the FET’s die area is larger and thus the effective input capacitance of the FET is increased. Often a 50% de- crease in Rds_On more than doubles the effective input gate charge, which must be supplied by the driver. The Rds_On power savings can be offset by the switching and dead-time losses with a suboptimum driver. While discrete solution can achieve reasonable drive capabil- ity, implementing shoot-through, programmable delay and other housekeeping functions necessary for safe opera- tion can become cumbersome and costly. The SC1405 family of parts presents a total solution for the high- speed, high power density applications. Wide input sup- ply range of 4.5V-25V allows use in battery powered ap- plications, new high voltage, distributed power servers as well as Class-D amplifiers. Theory of Operation The control input (CO) to the SC1405D is typically sup- plied by a PWM controller that regulates the power sup- ply output. (See Application Evaluation Schematic on page 12). The timing diagram demonstrates the sequence of events by which the top and bottom drive signals are applied. The shoot-through protection is implemented by holding the bottom FET off until the voltage at the phase node (intersection of top FET source, the output inductor and the bottom FET’s drain) has dropped below 1V. This assures that the top FET has turned off and that a direct current path does not exist between the input supply and ground, a condition which both the top and bottom FETs are on momentarily. The top FET is also prevented from turning on until the bottom FET is off. This time is internally set to 20ns (typical) and may be increased by adding a capacitor from the C-Delay pin to GND. The delay is approximately 1ns/pF in addition to the internal 20ns delay. The external capacitor may be needed if multiple High input capacitance FETs are used in parallel and the fall time is substantially greater than 20ns. It must be noted that increasing the dead-time by high values of C-Delay capacitor will reduce efficiency since the parallel Schottky or the bottom FET’s body diode will have to conduct during dead-time. Layout Guidelines As with any high speed , high current circuit, proper lay- out is critical in achieving optimum performance of the SC1405D. The Evaluation board schematic on page 12 shows a dual phase synchronous design with all surface mountable components. While components connecting to C-Delay, OVP_S, EN,S- MOD, DSPS_DR and PRDY are relatively noncritical, tight |
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