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HT47C10-1 Datasheet(PDF) 9 Page - Holtek Semiconductor Inc |
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HT47C10-1 Datasheet(HTML) 9 Page - Holtek Semiconductor Inc |
9 / 43 page HT47R10A-1/HT47C10-1 Rev. 1.10 9 September 27, 2007 Arithmetic and Logic Unit - ALU The ALU performs 8-bit arithmetic and logic operation. The ALU provides the following functions: · Arithmetic operations (ADD, ADC, SUB, SBC, DAA) · Logic operations (AND, OR, XOR, CPL) · Rotation (RL, RR, RLC, RRC) · Increment and Decrement (INC, DEC) · Branch decision (SZ, SNZ, SIZ, SDZ, etc.) The ALU not only saves the results of a data operation but also changes the status register. Status Register - STATUS This 8-bit register (0AH) contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF) and watchdog time-out flag (TO). It also records the status information and controls the operation sequence. With the exception of the TO and PDF flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status register will not change the TO or PDF flags. In addition it should be noted that operations related to the status register may give different results from those intended. The TO and PDF flags can only be changed by the Watchdog Timer overflow, system power-up, clearing the Watch- dog Timer and executing the ²HALT² instruction. The Z, OV, AC and C flags generally reflect the status of the latest operations. In addition, on entering the interrupt sequence or exe- cuting a subroutine call, the status register will not be automatically pushed onto the stack. If the contents of the status are important and if the subroutine can cor- rupt the status register, precautions must be taken to save it properly. Interrupts The HT47R10A-1/HT47C10-1 provides an external in- terrupt, an internal timer/event counter interrupt and an internal real time clock interrupt. The interrupt control register (INTC;0BH) contains the interrupt control bits to set the enable or disable and the interrupt request flags. When an interrupt subroutine is serviced, all other inter- rupts will be blocked by clearing the EMI bit. This scheme may prevent any further interrupt nesting. Other interrupt requests may occur during this interval, but only the interrupt request flag is recorded. If a certain in- terrupt needs servicing within the service routine, the EMI bit and the corresponding bit of the INTC may be set to allow interrupt nesting. If the stack is full, the inter- rupt request will not be acknowledged, even if the re- lated interrupt is enabled, until the SP is decremented. If immediate service is desired, the stack must be pre- vented from becoming full. All interrupts have a wake-up capability. As an interrupt is serviced, a control transfer occurs by pushing the pro- gram counter onto the stack and then by branching to subroutines at specified locations in the program mem- ory. Only the program counter is pushed onto the stack. If the contents of the accumulator and status register are altered by the interrupt service program, this may cor- rupt the desired control sequence, therefore their con- tents must be saved first. An external interrupt is triggered by a high to low transi- tion on the INT pin and the related interrupt request flag (EIF; bit 4 of INTC) will be set. When the interrupt is en- abled, and the stack is not full and the external interrupt is active, a subroutine call to location 04H will occur. The interrupt request flag, EIF, and EMI bits, will be cleared to disable other interrupts. Bit No. Label Function 0C C is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction. 1AC AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared. 2 Z Z is set if the result of an arithmetic or logic operation is 0; otherwise Z is cleared. 3OV OV is set if an operation results in a carry into the highest-order bit but not a carry out of the high- est-order bit, or vice versa; otherwise OV is cleared. 4 PDF PDF is cleared when either a system power-up or executing the ²CLR WDT² instruction. PDF is set by executing the ²HALT² instruction. 5TO TO is cleared by a system power-up or executing the ²CLR WDT² or ²HALT² instruction. TO is set by a WDT time-out. 6~7 ¾ Unused bit, read as ²0² STATUS (0AH) Register |
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