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HT48R52A Datasheet(PDF) 10 Page - Holtek Semiconductor Inc |
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HT48R52A Datasheet(HTML) 10 Page - Holtek Semiconductor Inc |
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10 / 36 page  HT48R52A Rev. 1.40 10 April 25, 2007 Interrupts, occurring in the interval between the rising edges of two consecutive T2 pulses, will be serviced on the latter of the two T2 pulses, if the corresponding inter- rupts are enabled. In the case of simultaneous requests the following table shows the priority that is applied. These can be masked by resetting the EMI bit. Interrupt Source Priority Vector External Interrupt 1 04H Timer/Event Counter Overflow 2 08H The timer/event counter interrupt request flag, TF, exter- nal interrupt request flag, EIF, enable timer/event coun- ter interrupt bit, ET, enable external interrupt bit, EEI, and enable master interrupt bit, EMI, constitute an inter- rupt control register, INTC, which is located at 0BH in the data memory. EMI, EEI, ETI are used to control the en- abling/disabling of interrupts. These bits prevent the re- quested interrupt from being serviced. Once the interrupt request flags, TF and EIF, are set, they will re- main in the INTC register until the interrupts are ser- viced or cleared by a software instruction. It is recommended that a program does not use the ²CALL subroutine² within the interrupt subroutine. Inter- rupts often occur in an unpredictable manner or need to be serviced immediately in some applications. If only one stack is left and enabling the interrupt is not well con- trolled, the original control sequence will be damaged if a ²CALL² is executed in the interrupt subroutine. Oscillator Configuration These devices provide two types of system oscillator cir- cuits, an RC oscillator and a 32768Hz crystal oscillator, the choice of which is determined by software. If an RC oscillator is used, an external resistor, whose resistance must range from 100k W to 2MW, should be connected between OSC1 and VSS. The RC oscillator provides the most cost effective solution, however, the frequency of oscillation may vary with VDD, tempera- tures and the chip itself due to process variations. It is, therefore, not suitable for timing sensitive operations where an accurate oscillator frequency is desired. The other oscillator circuit is designed for the real time clock. For this device, only a 32768Hz crystal oscillator can be used. The crystal should be connected between OSC3 and OSC4. The RTC oscillator circuit can be controlled to start up quickly by setting the ²QOSC² bit (bit 4 of mode). It is recommended to turn on the quick oscillating function at power on until the RTC oscillator is stable, and then turn it off after 2 seconds to reduce power consumption. The WDT oscillator is a free running on-chip RC oscilla- tor, and requires no external components. Although when the system enters the power down mode, the sys- tem clock stops, the WDT oscillator will keep running with a period of approximately 65 ms at 5V. The WDT os- cillator can be disabled by a configuration option to con- serve power. Watchdog Timer - WDT The WDT clock source is implemented by a internal WDT OSC, the external 32768Hz (fRTC) or the instruction clock (system clock divided by 4), the choice of which is deter- mined by configuration option. This timer is designed to prevent software malfunctions or sequences jumping to an unknown location with unpredictable results. The Watchdog can be disabled by a configuration option. If the Watchdog Timer is disabled, all the executions re- lated to WDT will result in no operation. If the device operates in a noisy environment, using the on-chip WDT OSC or 32768Hz crystal oscillator is strongly recommended. When the WDT clock source is selected, it will be first di- vided by 16 (4-stage), and then divided by the TMRC prescaler (8-stage), after that, divided by 512 (9-stage) to get the nominal time-out period. By using the TMRC prescaler, longer time-out periods can be realized. Writ- ing data to PSC2, PSC1, PSC0 can give different time-out periods. The WDT OSC period is 65 ms. This time-out period may vary with temperature, VDD and process variations. The WDT OSC keep running in any operation mode. If the instruction clock (system clock/4) is selected as the WDT clock source, the WDT operates in the same manner. 3 2 7 6 8 H z C r y s t a l O s c i l l a t o r R C O s c i l l a t o r O S C 1 4 7 0 p F V D D R O S C O S C 3 O S C 4 1 0 p F System Oscillator 4 - B i t D i v i d e r 8 - S t a g e P r e s c a l e r 8 - t o - 1 M U X W D T T i m e - o u t P S C 2 ~ P S C 0 O p t i o n S e l e c t S y s t e m C l o c k / 4 W D T O S C 3 2 7 6 8 H z f S 9 - B i t C o u n t e r Watchdog Timer |
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