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SC4205IS-2.5TRT Datasheet(PDF) 6 Page - Semtech Corporation |
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SC4205IS-2.5TRT Datasheet(HTML) 6 Page - Semtech Corporation |
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6 / 8 page  6 2004 Semtech Corp. www.semtech.com SC4205 POWER MANAGEMENT Introduction The SC4205 is intended for applications such as graphics cards where high current capability and very low dropout voltage are required. It provides a very simple, low cost solution that uses very little pcb real estate. Additional features include an enable pin to allow for a very low power consumption standby mode, and a fully adjustable output. Component Selection Input capacitor: a 4.7µF ceramic capacitor is recommended. This allows for the device being some distance from any bulk capacitance on the rail. Additionally, input droop due to load transients is reduced, improving load transient response. Additional capacitance may be added if required by the application. Output capacitor: a minimum bulk capacitance of 2.2µF, along with a 0.1µF ceramic decoupling capacitor is recommended. Increasing the bulk capacitance will improve the overall transient response. The use of multiple lower value ceramic capacitors in parallel to achieve the desired bulk capacitance will not cause stability issues. Although designed for use with ceramic output capacitors, the SC4205 is extremely tolerant of output capacitor ESR values and thus will also work comfortably with tantalum output capacitors. For refer- ence, the phase-margin contour of Figure 1 can be used to choose an appropriate output capacitor for a given stability requirement. Noise immunity: in very electrically noisy environments, it is recommended that 0.1µF ceramic capacitors be placed from IN to GND and OUT to GND as close to the device pins as possible. External voltage selection resistors: the use of 1% resistors, and designing for a current flow ≥ 10µA is recommended to ensure a well regulated output (thus R2 ≤ 120kΩ). Applications Information Thermal Considerations The power dissipation in the SC4205 is approximately equal to the product of the output current and the input to output voltage differential: () O D I VOUT VIN P • − ≈ The absolute worst-case dissipation is given by: () ) ( ) ( ) ( ) ( ) ( ) ( MAX Q MAX MAX O MIN MAX MAX D I VIN I VOUT VIN P • + • − = For a typical scenario, V IN = 3.3V ± 5%, VOUT = 2.8V and I O = 1A, therefore: V IN(MAX) = 3.465V, VOUT(MIN) = 2.744V and IQ(MAX) = 1.75mA, Thus P D(MAX) = 727mW. Using this figure, and assuming T A(MAX) = 70°C, we can calculate the maximum thermal impedance allowable to maintain T J ≤ 150°C: () () W C P T T R MAX D MAX A MAX J MAX A J TH / 110 727 . 70 150 ) ( ) ( ) ( ) )( ( ° = − = − = − This should be achievable for the SOIC-8EDP package using pcb copper area to aid in conducting the heat away, such as one square inch of copper connected to the pins of the device. Internal ground/power planes and air flow will also assist in removing heat. For higher ambient tem- peratures it may be necessary to use additional copper area. |
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