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SC4808C Datasheet(PDF) 8 Page - Semtech Corporation |
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SC4808C Datasheet(HTML) 8 Page - Semtech Corporation |
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8 / 24 page  8 2006 Semtech Corp. www.semtech.com SC4808C POWER MANAGEMENT SYNC/Bi-Phase operation In noise sensitive applications where synchronization of the oscillator frequency to a reference frequency is required, the SYNC pin can accept the external clock. By connecting an external control signal to the SYNC pin, the internal os- cillator frequency will be synchronized to the positive edge of the external control signal. SYNC is a positive edge trig- gered input with a threshold set to 1.0V (SC4808C). In a single controller operation, SYNC should be grounded or connected to an external synchronization clock within the SYNC frequency range. U2 SC4808 4 5 3 2 10 1 6 7 8 9 FB REF CS RC LUVLO SYNC GND OUTB OUTA VCC Cosc1 U1 SC4808 4 5 3 2 10 1 6 7 8 9 FB REF CS RC LUVLO SYNC GND OUTB OUTA VCC REF Rosc2 REF Rosc1 Cosc2 In the Bi-phase operation mode a very unique oscillator is utilized to allow two SC4808C’s to be synchronized together and work out of phase. This feature is set up by a simple connection of the SYNC input to the RC pin of the other part. The fastest oscillator automatically becomes the master, forcing the two PWMs to operate out of phase. This feature minimizes the input and output ripples, and reduces stress on the capacitors. Application Information (Cont.) FEED BACK The error signal from the output of an external error ampli- fier such as SC431 or SC4431 is applied to the inverting input of the PWM comparator at the FB pin either directly or via an opto coupler for the isolated applications. For best stability, keep the FB trace length as short as possible. C39 22n C38 0.1u Vref SC4431 1 2 4 5 R35 C36 C35 R34 R36 R38 C37 R32 Vout Vout C40 22pF R37 2.2k MOCD207 3 4 6 5 Vref FB The signal at the FB pin is then compared to the 3X ampli- fied signal from the current sense/ slope compensation CS pin. Matched out of phase signals are generated to control the OUTA and OUTB gate drives of the two phases. A single ramp signal is used to generate the control sig- nals for both phases, hence achieving a tightly matched per phase operation. Voltages below 1.5V at the FB pin, will produce a 0% duty cycle at the OUTA/OUTB gate drives. This offset is to pro- vide enough head room for the opto coupler used in iso- lated applications. GATE DRIVERS OUTA and OUTB are out of phase bipolar gate drive output stages, that are supplied from VCC and provide a peak source/sink current of about 100mA. Both stages are ca- pable of driving the logic input of external MOSFET drivers or a NPN/PNP transistor buffer. The output stages switch at half the oscillator frequency. When the voltage on the RC pin is rising, one of the two outputs is high, but during fall time, both outputs are off. This “dead time” between the two outputs, along with a slower output rise and fall time, insures that the two outputs can not be on at the same time. The dead time is programmable and depends upon the timing capacitor. OUTA (PWM1) OUTB (PWM1) OUTA (PWM2) OUTB (PWM2) |
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