Applications Information

Input Bias

Unused inputs should be biased or driven as shown in

Figure 5. This avoids noise coupling that might cause

toggling at the unused outputs.

Output Termination

Terminate open-emitter outputs (MAX9420/MAX9422)

through 50

termination. Terminate outputs using identical termina-

tion on each for the lowest output-to-output skew. When

a single-ended signal is taken from a differential output,

terminate both outputs. For example, if OUT_ is used as

a single-ended output, terminate both OUT_ and OUT_.

Ensure that the output currents do not exceed the cur-

rent limits as specified in the Absolute Maximum

Ratings table. Under all operating conditions, the

device’s total thermal limits should be observed.

Power-Supply Bypassing

Adequate power-supply bypassing is necessary to

maximize the performance and noise immunity. Bypass

face-mount ceramic 0.1µF and 0.01µF capacitors in

parallel as close to the device as possible, with the

0.01µF capacitor closest to the device pins. Use multi-

ple parallel vias for ground-plane connection to mini-

mize inductance.

Circuit Board Traces

Input and output trace characteristics affect the perfor-

mance of the MAX9420–MAX9423. Connect each of the

inputs and outputs to a 50

Ω characteristic impedance

trace. Avoid discontinuities in differential impedance

and maximize common-mode noise immunity by main-

taining the distance between differential traces and

avoid sharp corners. Minimize the number of vias to

prevent impedance discontinuities. Reduce the reflec-

tions by maintaining 50

Ω characteristic impedance

through connectors and across cables. Minimize skew

by matching the electrical length of the traces.

Chip Information

TRANSISTOR COUNT: 927

PROCESS: Bipolar

Quad Differential LVECL-to-LVPECL Translators

8

_______________________________________________________________________________________

Figure 4. CLK-to-OUT Propagation Delay Timing Diagram

CLK

CLK

IN_

IN_

OUT_

OUT_

SEL = LOW

EN = HIGH