Detailed Description

The MAX9420–MAX9423 are extremely fast, low-skew

quad LVECL-to-LVPECL translators designed for high-

speed signal and clock driver applications. The

devices feature ultra-low propagation delay of 336ps

and channel-to-channel skew of 17ps.

The four channels can be operated synchronously with

an external clock, or in asynchronous mode, deter-

mined by the state of the SEL input. An enable input

provides the ability to force all the outputs to a differen-

tial low state.

These devices operate with a negative supply voltage

of -2.0V to -3.6V, compatible with LVECL input signals.

The positive supply range is 2.375V to 3.6V for differen-

tial LVPECL output signals.

A variety of input and output terminations are offered

for maximum design flexibility. The MAX9420 has open

inputs and open-emitter outputs. The MAX9421 has

open inputs and 50

Ω series outputs. The MAX9422 has

100

Ω differential input impedance and open-emitter

outputs. The MAX9423 has 100

Ω differential input

impedance and 50

Ω series outputs.

Supply Voltages

For interfacing to differential LVECL input levels, the

range is from 2.375V to 3.6V, compatible with LVPECL

Data Inputs

The MAX9420/MAX9421 have open inputs and require

external termination. The MAX9422/MAX9423 have inte-

grated 100

Ω differential input termination resistors from

IN_ to IN_, reducing external component count.

Outputs

The MAX9421/MAX9423 have internal 50

Ω series out-

put termination resistors and 8mA internal pulldown

current sources. Using integrated resistors reduces

external component count.

The MAX9420/MAX9422 have open-emitter outputs. An

external termination is required. See the Output

Termination section.

Enable

Setting EN = high and EN = low enables the device.

Setting EN = low and EN = high forces the outputs to a

differential low. All changes on CLK, SEL, and IN_ are

ignored.

Asynchronous Operation

Setting SEL = high and SEL = low enables the four

channels to operate independently as LVECL-to-

LVPECL translators. The CLK signal is ignored in this

mode. In asynchronous mode, the CLK signal should

be set to either logic low or high state to minimize noise

coupling.

Synchronous Operation

Setting SEL = low and SEL = high enables all four

channels to operate in synchronized mode. In this

mode, buffered inputs are clocked into flip-flops simul-

taneously on the rising edge of the differential clock

input (CLK and CLK).

Differential Signal Input Limit

The maximum signal magnitude of all the differential

inputs is 3.0V.

Quad Differential LVECL-to-LVPECL Translators

6

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GND

GND

INPUT VOLTAGE DEFINITION

OUTPUT VOLTAGE DEFINITION

Figure 1. Input and Output Voltage Definitions