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AD9863BCPRL-50 Datasheet(PDF) 8 Page - Analog Devices |
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AD9863BCPRL-50 Datasheet(HTML) 8 Page - Analog Devices |
8 / 40 page AD9863 Rev. A| Page 8 of 40 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 SPI_DIO 1 SPI_CLK 2 SPI_SDO 3 ADC_LO_PWR 4 DVDD 5 DVSS 6 AVDD 7 IOUT–A 8 IOUT+A 9 AGND 10 REFIO 11 FSADJ 12 AGND 13 IOUT+B 14 IOUT–B 15 AVDD 16 CLKIN1 48 CLKIN2 47 RESET 46 L0 45 L1 44 L2 43 L3 42 L4 41 L5 40 L6 39 L7 38 L8 37 L9 36 L10 35 L11 34 IFACE1 33 AD9863 TOP VIEW (Not to Scale) Figure 3. Pin Configuration Table 8. Pin Function Descriptions Pin No. Name1 Description2, 3 1 SPI_DIO (Interp1) SPI: Serial Port Data Input. No SPI: Tx Interpolation Pin, MSB. 2 SPI_CLK (Interp0) SPI: Serial Port Shift Clock. No SPI: Tx Interpolation Pin, LSB. 3 SPI_SDO (FD/HD) SPI: 4-Wire Serial Port Data Output. No SPI: Configures Full-Duplex or Half-Duplex Mode. 4 ADC_LO_PWR ADC Low Power Mode Enable. Defined at power-up. 5, 31 DVDD, DRVDD Digital Supply. 6, 32 DVSS, DRVDD Digital Ground. 7, 16, 50, 51, 61 AVDD Analog Supply. 8, 9 IOUT −A, IOUT+A DAC A Differential Output. 10, 13, 49, 53, 59 AGND, AVSS Analog Ground. 11 REFIO Tx DAC Band Gap Reference Decoupling Pin. 12 FSADJ Tx DAC Full-Scale Adjust Pin. 14, 15 IOUT+B, IOUT−B DAC B Differential Output. SPI: Buffered CLKIN. Can be configured as system clock output. 17 IFACE2 (12/24) No SPI: Buffered CLKIN for FD; 12/24 configuration pin for HD24 or HD12. 18 IFACE3 Clock Output. 19 to 30 U11 to U0 Upper Data Bit 11 to Upper Data Bit 0. SPI: TxSYNC for FD; Tx/Rx for HD24, HD12, or clone. 33 IFACE1 No SPI: FD >> TxSYNC; HD24 or HD12: Tx/Rx. Clone mode requires a serial port interface. 34 to 45 L11 to L0 Lower Data Bit 11 to Lower Data Bit 0. 46 RESET Chip Reset When Low. 47 CLKIN2 Clock Input 2. 48 CLKIN1 Clock Input 1. |
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